In-service reconfigurable DRAM and flash memory device
First Claim
1. A memory cell comprising:
- a vertical dynamic random access memory cell that comprises a control gate formed vertically between a pair of source/drain regions doped into a substrate; and
a vertical non-volatile memory cell coupled to the dynamic random access memory cell through a first of the pair of source/drain regions and a floating body area in the substrate.
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Accused Products
Abstract
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.
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Citations
26 Claims
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1. A memory cell comprising:
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a vertical dynamic random access memory cell that comprises a control gate formed vertically between a pair of source/drain regions doped into a substrate; and a vertical non-volatile memory cell coupled to the dynamic random access memory cell through a first of the pair of source/drain regions and a floating body area in the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory cell comprising:
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a vertical dynamic random access memory cell comprising; a pair of source/drain regions in a substantially vertical configuration; and a vertical control gate formed substantially between the pair of source/drain regions; and a vertical flash memory cell coupled to the dynamic random access memory cell, the flash memory cell comprising; a pair of source/drain regions in a substantially vertical configuration, wherein a first source/drain region is shared with the pair of source/drain regions of the dynamic random access memory cell; a vertical floating gate formed substantially between the pair of source/drain regions; and a vertical control gate formed over the vertical floating gate. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. An electronic system comprising:
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a processor for generating memory control signals; and a memory array that is selectable between volatile and non-volatile memory functions in response to the memory control signals, the array comprising a plurality of memory cells comprising; a vertical dynamic random access memory cell that comprises a control gate formed vertically between a pair of source/drain regions doped into a substrate; and a vertical non-volatile memory cell coupled to the dynamic random access memory cell through a first of the pair of source/drain regions and a floating body area. - View Dependent Claims (24, 25, 26)
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Specification