In-service reconfigurable DRAM and flash memory device

• US 7,190,616 B2
• Filed: 07/19/2004
• Issued: 03/13/2007
• Est. Priority Date: 07/19/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A., Forbes, Leonard
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US10/894,101
• Publication Number:
  US 20060013042A1
• Time in Patent Office: 967 Days
• Field of Search: 365/185.05, 365/185.08, 365/185.33, 365/185.261, 365/185.17, 365/185.01, 257/304
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.

Claims

1. A memory cell comprising:

a vertical dynamic random access memory cell that comprises a control gate formed vertically between a pair of source/drain regions doped into a substrate; and

a vertical non-volatile memory cell coupled to the dynamic random access memory cell through a first of the pair of source/drain regions and a floating body area in the substrate.

2. The memory cell of claim 1 wherein the first source/drain region is an n+ drain region.

3. The memory cell of claim 1 wherein the first source/drain region is a p-drain region.

4. The memory cell of claim 1 wherein the substrate is a compound semiconductor.

5. The memory cell of claim 4 wherein the compound semiconductor is gallium arsenide.

6. The memory cell of claim 1 wherein the substrate is germanium.

7. The memory cell of claim 1 wherein the substrate is carbon.

8. The memory cell of claim 1 wherein the substrate is a silicon-on-insulator substrate.

9. The memory cell of claim 1 wherein the dynamic random access memory cell is comprised of a floating body transistor.

10. The memory cell of claim 1 wherein the non-volatile memory cell is comprised of a floating gate transistor.

11. The memory cell of claim 1 wherein the non-volatile memory cell is a nitride read only memory (NROM) cell.

12. The memory cell of claim 1 wherein the pair of source/drain regions are n+ conductivity regions in a p-type substrate.

13. The memory cell of claim 1 and further including a first wordline coupled to the non-volatile memory cell, a second wordline coupled to the dynamic random access memory cell, and a bitline coupled to the doped region.

14. A memory cell comprising:

a vertical dynamic random access memory cell comprising;

a pair of source/drain regions in a substantially vertical configuration; and

a vertical control gate formed substantially between the pair of source/drain regions; and

a vertical flash memory cell coupled to the dynamic random access memory cell, the flash memory cell comprising;

a pair of source/drain regions in a substantially vertical configuration, wherein a first source/drain region is shared with the pair of source/drain regions of the dynamic random access memory cell;

a vertical floating gate formed substantially between the pair of source/drain regions; and

a vertical control gate formed over the vertical floating gate.

15. The cell of claim 14 and further including a floating body area formed in a pillar of a silicon substrate and substantially between the dynamic random access memory cell and the flash memory cell, the first source/drain region of the pair of source/drain regions located at the top of the pillar and the second source/drain region located at the bottom of trenches in the substrate formed around the pillar.

16. The cell of claim 14 and further including a DRAM wordline coupled to the control gate of the dynamic random access memory cell, a flash address/wordline coupled to the control gate of the flash memory cell, and wherein the first source/drain region is coupled to a memory array bitline, and the second source/drain regions of both the dynamic random access memory cell and the flash memory cell coupled to ground.

17. The cell of claim 14 and further including a DRAM wordline coupled to the control gate of the dynamic random access memory cell wherein the control gate of the flash memory cell is coupled to ground, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the dynamic random access memory cell is coupled to a source line.

18. The cell of claim 14 and further including a DRAM wordline coupled to the control gate of the dynamic random access memory cell wherein the control gate of the flash memory cell is coupled to a negative bias voltage, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the dynamic random access memory cell is coupled to a memory array source line.

19. The cell of claim 14 and further including a DRAM wordline coupled to the control gate of the dynamic random access memory cell wherein the control gate of the flash memory cell is coupled to ground, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the dynamic random access memory cell is coupled to ground.

20. The cell of claim 14 and further including a wordline coupled to the control gate of the flash memory cell wherein the control gate of the dynamic random access memory cell is coupled to ground, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the flash memory cell is coupled to a memory array source line.

21. The cell of claim 14 and further including a wordline coupled to the control gate of the flash memory cell wherein the control gate of the dynamic random access memory cell is coupled to ground, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the flash memory cell is coupled to ground.

22. The cell of claim 14 and further including a DRAM wordline coupled to the control gate of the dynamic random access memory cell wherein the control gate of the flash memory cell is coupled to a positive transient bias, the first source/drain region is coupled to a memory array bitline, and the second source/drain region of the dynamic random access memory cell is coupled to a source line.

23. An electronic system comprising:

a processor for generating memory control signals; and

a memory array that is selectable between volatile and non-volatile memory functions in response to the memory control signals, the array comprising a plurality of memory cells comprising;

a vertical dynamic random access memory cell that comprises a control gate formed vertically between a pair of source/drain regions doped into a substrate; and

a vertical non-volatile memory cell coupled to the dynamic random access memory cell through a first of the pair of source/drain regions and a floating body area.

24. The system of claim 23 wherein the processor is adapted to generate a memory control signal that selects a dynamic random access memory mode.

25. The system of claim 23 wherein the non-volatile memory cell is a flash memory cell and the processor is adapted to generate a memory control signal that selects a flash memory mode.

26. The system of claim 23 wherein the non-volatile memory cell is a nitride read only memory (NROM) cell and the processor is adapted to generate a memory control signal that selects an NROM mode.