Flash EEprom system

• US 7,190,617 B1
• Filed: 06/23/1998
• Issued: 03/13/2007
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US09/103,056
• Time in Patent Office: 3,185 Days
• Field of Search: 365/185.01, 365/185.33, 365/185.29, 365/185.11, 365/230.01, 365/230.03, 711/202, 711/209, 711/221
• US Class Current: 365/185.11
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A system of Flash EEprom chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A storage device employing a flash memory, wherein a storage area of said storage device is divided into a plurality of physical sectors identified by physical addresses, said storage device includes:

logical address conversion means which receives a logical address of data in a data writing operation and converts said logical address into a physical address, and

a memory controller for receiving said physical address resulting from the conversion by the conversion means, and writing said data into a respective physical sector;

wherein said logical address conversion means converts a logical address received in the writing operation to the physical address which is different from the physical address to which said logical address conversion means converted a logical address, identical to the logical address to be presently converted, in a preceding writing operation.

2. A storage device employing a flash memory according to claim 1, further comprising:

a write sector pointer for storing said physical address of the physical sector into which data should be written in the next data writing operation,

wherein said logical address conversion means converts said logical address into said physical address stored in said write sector pointer.

3. A storage device employing a flash memory according to claim 1, wherein the storage area includes an array of memory cells that are individually programmable into exactly two states in order to store exactly one bit of data per cell.

4. A storage device employing a flash memory according to claim 1, wherein the storage area includes an array of memory cells that are individually programmable into more than two states in order to store more than one bit of data per cell.