Methods for forming an array of MEMS optical elements

• US 7,190,854 B1
• Filed: 07/06/2005
• Issued: 03/13/2007
• Est. Priority Date: 05/24/2000
• Status: Expired due to Term

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Active Optical Networks, Inc.
• Inventors: Novotny, Vlad J., Dhillon, Parvinder
• Primary Examiner(s): Bovernick; Rodney
• Assistant Examiner(s): STAHL, MICHAEL J
• Application Number:
  US11/176,711
• Time in Patent Office: 615 Days
• Field of Search: None
• US Class Current: 385/18
• CPC Class Codes: G02B 6/3518 the reflective optical element being an intrinsic part of a MEMS device, i.e. fabricated together with the MEMS device MEMS devices in general B81B; manufacture of MEM devices in general B81C; micromechanical devices controlling the direction of light G02B26/0833
• CPC Class Codes: G02B 6/3556 NxM switch, i.e. regular arrays of switches elements of matrix type constellation
• CPC Class Codes: G02B 6/357 Electrostatic force electrostatic forces controlling reflecting elements in general G02B26/0841
• CPC Class Codes: G02B 6/3584 constructional details of an associated actuator having a MEMS construction, i.e. constructed using semiconductor technology such as etching MEMS per se B81B, B81C

Abstract

An embodiment of the invention comprises an optical element capable of motion in at least one degree of freedom wherein the motion in at least one degree of freedom is enabled by serpentine hinges configured to enable the optical element to move in at least one degree of freedom. The embodiment further includes driving elements configured to deflect the optical element in said at least one degree of freedom to controllably induce deflection in the optical element and a damping element to reduce magnitude of resonances. Another embodiment includes a MEMS optical apparatus comprising an optical element capable of motion in two degrees of freedom. The two degrees of freedom are enabled by two pairs of serpentine hinges. A first pair of serpentine hinges is configured to enable the optical element to move in one degree of freedom and a second pair of serpentine hinges is configured to enable the optical element to move in a second degree of freedom. The apparatus further includes driving elements configured to deflect the optical element in said two degrees of freedom and a damping element to reduce magnitude of resonances. The invention includes method embodiments for forming arrays of MEMS optical elements including reflector arrays.

Claims

1. A method for forming an array of MEMS optical elements, the method comprising:

providing a single crystal silicon on insulator (SOI) wafer having a layered structure comprising a silicon wafer layer having an internal oxide layer formed thereon and having a device silicon layer formed on the internal oxide layer, wherein a top surface of the device silicon layer has formed thereon a top oxide layer, and wherein the bottom surface of the silicon wafer layer has formed thereon a bottom oxide layer;

forming a bottom photoresist layer on the bottom oxide film layer having openings defining a bottom pocket;

forming a top photoresist layer on the top oxide film layer having openings defining a hinge region and open regions;

removing the top oxide layer in the hinge and open regions defined by the openings in the top photoresist layer to expose the hinge region of the device silicon layer;

forming a second photoresist layer on a top surface of the SOI wafer, the second photoresist layer patterning the hinge region of the device silicon layer so that a hinge can be formed;

etching the patterned hinge region to remove portions of the device silicon layer forming recessed portions defining the hinge;

removing the second photoresist layer, thereby exposing the underlying top oxide layer as a hard mask layer having openings in the hinge and open regions;

etching the device silicon layer through the openings in the hard mask wherein the recessed portions are etched until the internal oxide layer is reached, and wherein the unetched surfaces are partially etched leaving a portion of the unetched surfaces in place to define a thickness of the hinge;

etching the bottom surface of the SOI wafer through openings in the bottom oxide layer to remove material from the silicon wafer layer to form a pocket region defining a movable optical element supported by the hinge; and

etching the SOI wafer to remove the internal oxide layer in the pocket region.

2. The method of claim 1, further comprising etching material from a separation line region between adjacent optical elements to enable the array to be separated into a plurality of smaller arrays.

3. The method of claim 2, wherein etching material from a separation line region comprises the operations of dry etching to remove material from the separation line region;

laser cutting in the separation line region; and

cleaving in the separation line region into separate arrays of desired sizes.

4. The method of claim 2, wherein etching material from a separation line region comprises the operations of laser cutting in the separation line region and cleaving in the separation line region into separate arrays of desired sizes.

5. The method of claim 4 wherein etching material from a separation line region comprises the operations of dry etching to remove material from the separation line region and cleaving in the separation line region into separate arrays of desired sizes.

6. The method of claim 4 further comprising assembling the separated arrays with another wafer having formed thereon appropriate driving elements and control circuitry, and packaging the assembled arrays.

7. The method of claim 6 wherein packaging the assembled arrays comprises hermetically packaging the assembled arrays.

8. A method for forming an array of MEMS optical elements, the method comprising:

providing a wafer having top surface and a bottom surface, the top surface having formed thereon a top insulating layer and the bottom surface having formed thereon a bottom insulating layer;

forming a bottom mask layer on the bottom oxide film layer having openings defining a bottom pocket;

forming a top mask layer on the top insulating layer having openings defining hinge regions and open structures;

first etching to remove the top insulating layer in hinge and open regions defined by the openings in the top mask layer exposing a hinge region;

forming a second mask layer on the top surface, the second mask layer patterning the hinge region so that a hinge can be formed;

second etching the patterned hinge region and open region to form a hinge in the wafer;

removing the second mask layer, thereby exposing the underlying top insulating layer as a hard mask layer having openings in the hinge and open regions;

third etching the wafer through the openings in the hard mask wherein the recessed portions are etched in a timed etch leaving a portion of the unetched surfaces in place as hinges, thereby defining hinge thickness;

fourth etching the bottom surface of the wafer through openings in the bottom oxide layer to remove material from the silicon wafer to form a pocket region defining a movable optical element supported by hinges; and

forming a reflective layer on at least one surface of the movable optical element.

9. The method of claim 8 further including a fifth etching to remove material from a separation line region thereby enabling the structure to be separated into arrays of a desired size.

10. The method of claim 9 wherein the operation of fifth etching comprises the operations of dry etching to remove material from the separation line region;

laser cutting in the separation line region; and

cleaving in the separation line region into separate arrays of desired sizes.

11. The method of claim 9 wherein the operation of fifth etching comprises the operations of laser cutting in the separation line region;

and cleaving in the separation line region into separate arrays of desired sizes.

12. The method of claim 9 wherein the operation of fifth etching comprises the operations of dry etching to remove material from the separation line region;

and cleaving in the separation line region into separate arrays of desired sizes.

13. The method of claim 9 further comprising assembling the separated arrays with another wafer having formed thereon appropriate driving elements and control circuitry, and packaging the assembled arrays.