Method and system for short-circuit current modeling in CMOS integrated circuits

• US 7,191,113 B2
• Filed: 12/17/2002
• Issued: 03/13/2007
• Est. Priority Date: 12/17/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nassif, Sani Richard, Acar, Emrah, Arunachalam, Ravishankar
• Primary Examiner(s): Shah; Kamini
• Assistant Examiner(s): GEBRESILASSIE, KIBROM K
• Application Number:
  US10/322,089
• Publication Number:
  US 20040117169A1
• Time in Patent Office: 1,547 Days
• Field of Search: 703/15, 703/14, 703/19, 703/18, 702/59, 702/60, 702/64, 702/70, 702/79, 716/5, 716/17, 716/18
• US Class Current: 703/15
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device. One or more short-circuit current points can be determined from the model and used to generate a polygonal waveform model of the short-circuit current, or can be used along with the width (period) of the waveform to calculate short-circuit power dissipation directly.

Claims

1. A method for modeling characteristics of a logical circuit, comprising:

receiving input of a first plurality of values corresponding to points on an input voltage waveform of said logical circuit at discrete times, wherein said first plurality of values is a non-linear representation of said input voltage waveform;

receiving input of a second plurality of values corresponding to points on an output voltage waveform of said logical circuit at said discrete times;

selecting a particular one of said plurality of short-circuit current values;

calculating a plurality of short-circuit current values forming a polygonal model of current through a given one of a complementary pair of transistors within said logical circuit for said discrete times in conformity with a model of said given transistor, a corresponding one of said first plurality of values, and a corresponding one of said second plurality of values, wherein a peak value of said polygonal model is equal to said selected particular one of said plurality of short-circuit current values, and wherein said polygonal model has a width equal to a time difference between a last one of said discrete times and a first one of said discrete times; and

displaying a result of said calculating.

2. The method of claim 1, further comprising selecting said given one of said complementary pair of transistors in conformity with a transition direction of said input voltage waveform.

3. The method of claim 1, further comprising generating said polygonal model as a triangular model of said short-circuit current having an apex equal to said selected short-circuit current value.

4. The method of claim 3, further comprising calculating a short-circuit power dissipation as one half of the product of said selected short-circuit current value and a power supply voltage of said logic circuit divided by said time difference.

5. The method of claim 3, wherein said logic circuit comprises a plurality of complementary circuits, wherein said triangular model is generated for said plurality of complementary circuits and further comprising summing said plurality of triangular models to determine a total short-circuit current for a power distribution network of said logic circuit.

6. The method of claim 3, wherein said selected short-circuit current value is a maximum short-circuit current value.

7. The method of claim 3, wherein said selected short-circuit current value is a short-circuit current value for which said given transistor has entered saturation.

8. The method of claim 1, further comprising:

selecting another one of said plurality of short-circuit current values corresponding to a short-circuit current value for which said at least one transistor has entered saturation; and

generating said polygonal model as a trapezoidal model of said short-circuit current conforming to both of said selected short-circuit current values.

9. The method of claim 1, further comprising:

piecewise-integrating a result of said calculating; and

multiplying a result of said integrating by a power supply voltage to determine a power dissipation.

10. A computer program product for use with a workstation computer, wherein said computer program product comprises a storage media containing program instructions for execution within said workstation computer for modeling characteristics of a logical circuit, and wherein said program instructions comprise program instructions for:

receiving input of a first plurality of values corresponding to points on an input voltage waveform of said logical circuit at discrete times, wherein said first plurality of values is a non-linear representation of said input voltage waveform;

receiving input of a second plurality of values corresponding to points on an output voltage waveform of said logical circuit at said discrete times;

selecting a particular one of said plurality of short-circuit current values;

calculating a plurality of short-circuit current values forming a polygonal model of current through a given one of a complementary pair of transistors within said logical circuit for said discrete times in conformity with a model of said given transistor, a corresponding one of said first plurality of values, and a corresponding one of said second plurality of values, wherein a peak value of said polygonal model is equal to said selected particular one of said plurality of short-circuit current values, and wherein said polygonal model has a width equal to a time difference between a last one of said discrete times and a first one of said discrete times; and

displaying a result of said calculating.

11. The computer program product of claim 10, wherein said program instructions further comprise program instructions for said given one of said complementary pair of transistors in conformity with a transition direction of said input voltage waveform.

12. The computer program product of claim 10, wherein said program instructions further comprise program instructions for generating said polygonal model as a triangular model of said short-circuit current having an apex equal to said selected short-circuit current value.

13. The computer program product of claim 12, wherein said program instructions further comprise program instructions for calculating a short-circuit power dissipation as one half of the product of said selected short-circuit current value and a power supply voltage of said logic circuit divided by said time difference.

14. The computer program product of claim 12, wherein said logic circuit comprises a plurality of complementary circuits, wherein said program instructions for generating generate triangular models for said plurality of complementary circuits and further comprising program instructions for summing said plurality of triangular models to determine a total short-circuit current for a power distribution network of said logic circuit.

15. The computer program product of claim 12, wherein said selected short-circuit current value is a maximum short circuit current value.

16. The computer program product of claim 12, wherein said selected short-circuit current value is a short-circuit current value for which said at least one transistor has entered saturation.

17. The computer program product of claim 10, wherein said program instructions further comprise program instructions for:

selecting another one of said plurality of short-circuit circuit current values corresponding to a short-circuit current value for which said at least one transistor has entered saturation; and

generating said polygonal model as a trapezoidal model of said short-circuit current conforming to both of said selected short-circuit current values.

18. The computer program product of claim 10, wherein said program instructions further comprise program instructions for:

piecewise-integrating a result of said calculating; and

multiplying a result of said integrating by a power supply voltage to determine a power dissipation.

19. A workstation comprising:

a memory for storing program instructions and data values for modeling characteristics of a logical circuit;

a processor for executing said program instructions, wherein said program instructions comprise program instructions for

receiving input of a first plurality of values corresponding to points on an input voltage waveform of said logical circuit at discrete times, wherein said first plurality of values is a non-linear representation of said input voltage waveform;

receiving input of a first plurality of values corresponding to points on an input voltage waveform of said logical circuit at discrete times, wherein said first plurality of values is a non-linear representation of said input voltage waveform;

receiving input of a second plurality of values corresponding to points on an output voltage waveform of said logical circuit at said discrete times;

selecting a particular one of said plurality of short-circuit current values;

calculating a plurality of short-circuit current values forming a polygonal model of current through a given one of a complementary pair of transistors within said logical circuit for said discrete times in conformity with a model of said given transistor, a corresponding one of said first plurality of values, and a corresponding one of said second plurality of values, wherein a peak value of said polygonal model is equal to said selected particular one of said plurality of short-circuit current values, and wherein said polygonal model has a width equal to a time difference between a last one of said discrete times and a first one of said discrete times; and

displaying a result of said calculating.

20. The workstation of claim 19, wherein said program instructions further comprise program instructions for said given one of said complementary pair of transistors in conformity with a transition direction of said input voltage waveform.

21. The workstation of claim 19, wherein said program instructions further comprise program instructions for generating said polygonal model as a triangular model of said short-circuit current having an apex equal to said selected short-circuit current value.

22. The workstation of claim 19, wherein said program instructions further comprise program instructions for calculating a short-circuit power dissipation as one half of the product of said selected short-circuit current value and a power supply voltage of said logic circuit divided by said time difference.

23. The workstation of claim 21, wherein said logic circuit comprises a plurality of complementary circuits, wherein said program instructions for generating generate triangular models for said plurality of complementary circuits and further comprising program instructions for summing said plurality of triangular models to determine a total short-circuit current for a power distribution network of said logic circuit.

24. The workstation of claim 21, wherein said selected short-circuit current value is a maximum short-circuit current value.

25. The workstation of claim 21, wherein said selected short-circuit current value is a short-circuit current value for which said at least one transistor has entered saturation.

26. The workstation of claim 19, wherein said program instructions further comprise program instructions for:

selecting another one of said plurality of short-circuit circuit current values corresponding to a short-circuit current value for which said at least one transistor has entered saturation; and

generating said polygonal model as a trapezoidal model of said short-circuit current conforming to both of said selected short-circuit current values.

27. The workstation of claim 19, wherein said program instructions further comprise program instructions for:

piecewise-integrating a result of said calculating; and

multiplying a result of said integrating by a power supply voltage to determine a power dissipation.