Fast-path apparatus for receiving data corresponding to a TCP connection

• US 7,191,241 B2
• Filed: 09/27/2002
• Issued: 03/13/2007
• Est. Priority Date: 09/27/2002
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Blightman, Stephen E. J., Starr, Daryl D.
• Primary Examiner(s): Walsh; John B.
• Application Number:
  US10/260,959
• Publication Number:
  US 20040064589A1
• Time in Patent Office: 1,628 Days
• Field of Search: None
• US Class Current: 709/230
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Claims

1. A system comprising:

a host containing a central processing unit (CPU) that establishes a Transmission Control Protocol (TCP) Control Block (TCB); and

a device coupled to the host as an interface, the device including a first processor that TCP processes a first TCP header that is contained in a first message packet, the device including a second processor that TCP processes a second TCP header that is contained in a second message packet, such that the first processor updates the TCB in accordance with processing the first TCP header.

2. The system of claim 1, wherein the first TCP header is TCP processed by the first processor at the same time that the second TCP header is TCP processed by the second processor.

3. The system of claim 1, wherein the first processor is pipelined with the second processor.

4. The system of claim 1, wherein the first processor is a receive processor and the second processor is a transmit processor.

5. The system of claim 1, wherein the device includes a receive sequencer coupled to at least one of said processors.

6. The system of claim 1, wherein the device includes a transmit sequencer coupled to at least one of said processors.

7. The system of claim 1, wherein the second packet corresponds to the TCB.

8. The system of claim 1, wherein the second packet corresponds to a second TCB.

9. The system of claim 1, wherein the device is coupled to the host with a Peripheral Component Interface (PCI) bus.

10. A system comprising:

a host containing a central processing unit (CPU) that establishes a Transmission Control Protocol (TCP) Control Block (TCB); and

a device coupled to the host as an interface, the device including a first mechanism that protocol processes a receive packet, the receive packet containing a first TCP header, the device including a second mechanism that protocol processes a transmit packet, the transmit packet containing a second TCP header, wherein one of the mechanisms updates the TCB to reflect the processing of one of the packets.

11. The system of claim 10, wherein the first mechanism includes a first processor and the second mechanism includes a second processor.

12. The system of claim 11, wherein the first processor is pipelined with the second processor.

13. The system of claim 10, wherein the first mechanism includes a receive processor and the second mechanism includes a transmit processor, the receive processor TCP processing the first TCP header and the transmit processor TCP processing the second TCP header.

14. The system of claim 10, wherein the device includes a receive sequencer that classifies the first header as corresponding to TCP.

15. The system of claim 10, wherein the device includes a transmit sequencer that prepends the second TCP header to the transmit packet.

16. The system of claim 10, wherein the device is coupled to the host with a Peripheral Component Interface (PCI) bus.

17. The system of claim 10, wherein the device acquires the TCB from the CPU.

18. The system of claim 10, wherein the other of the packets corresponds to a second TCB.

19. A system comprising:

a host containing a central processing unit (CPU) that establishes a Transmission Control Protocol (TCP) connection; and

a network interface device coupled to the host, the network interface device including a first processor that processes a first packet to update the TCP connection, the network interface device including a second processor that processes a second packet to update the TCP connection, the network interface device including header processing hardware to parse the first packet and determine that the first packet includes a TCP header.

20. The system of claim 19, wherein the first processor is a receive processor and the second processor is a transmit processor.

21. The system of claim 19, wherein the header processing hardware is a receive sequencer.

22. The system of claim 19, further comprising a transmit sequencer coupled to at least one of said processors.

23. The system of claim 19, wherein the device is coupled to the host with a Peripheral Component Interface (PCI) bus.

24. The system of claim 19, wherein control of the TCP connection passes from the first processor to the second processor.

25. The system of claim 19, wherein the first processor processes a third packet that corresponds to a second TCP connection.