High-throughput UART interfaces

• US 7,191,262 B2
• Filed: 10/03/2003
• Issued: 03/13/2007
• Est. Priority Date: 10/14/2002
• Status: Expired due to Fees

• Current Assignee: ELAN Trading Limited
• Original Assignee: Elan Digital Systems Ltd.
• Inventors: Sleeman, Peter T
• Primary Examiner(s): Nguyen; Tanh Q.
• Application Number:
  US10/678,847
• Publication Number:
  US 20040085996A1
• Time in Patent Office: 1,257 Days
• Field of Search: 370/464, 370/465, 370/106, 370/261, 370/278, 370/282, 710/2, 710/8, 710/11, 710/14, 710/15, 710/16, 710/38, 710/52, 710 63- 64, 710 71- 74, 703 23- 25, 703/27, 375/219, 375/220, 375/222, 455/557, 455/558
• US Class Current: 710/62
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 76/10 Connection setup

Abstract

A modified universal asynchronous receiver transmitter (UART) device is provided with an auxiliary high speed parallel channel using supplementary FIFO buffers for the exchange of data. The auxiliary parallel channel is separate from the normal lower speed serial channel which is retained in unmodified form. The retained serial channel provides full compatibility with and support for the National Semiconductor 16550 standard, while the auxiliary parallel channel allows for rapid transfer of large data blocks, such as is needed for a PCMCIA wireless data card for example. The key advantages of this approach lie both in the data transfer speed and in the reduced amount of development time needed to implement a UART interface for communicating between a host computer and a new subsystem. This is because all the UART functions, except large volume data transfer, can be carried out over the standard serial channel using standard device drivers.

Claims

1. An interface device for enabling communications between a host and a subsystem, comprising:

(a) a register set consisting of a plurality of standard UART registers, the register set being configurable to control host-subsystem communications;

(b) a host interface configurable to establish data communication with the host;

(c) a serial interface configurable to establish a bi-directional serial data communication channel to the subsystem under control of the register set; and

(d) a parallel interface configurable to establish an auxiliary parallel data communication channel to the subsystem, the parallel data communication channel being operable in conjunction with the serial data communication channel, wherein the parallel interface operates under control of the register set.

2. An interface device according to claim 1, further comprising a supplementary data buffer for writing and/or reading data to and/or from the subsystem via the parallel interface.

3. An interface device according to claim 2, wherein one of the registers is mapped to the data buffer so that accesses to the mapped register will cause accesses to the data buffer.

4. An interface device according to claim 2, wherein the data buffer is a FIFO buffer.

5. An interface device according to claim 1, further comprising supplementary data buffers for writing and reading data to and from the subsystem via the parallel interface.

6. An interface device according to claim 5, wherein one of the registers is mapped to at least one of the supplementary data buffers so that accesses to the mapped register will cause accesses to the at least one of the supplementary data buffers.

7. An interface device according to claim 5, wherein the data buffers are FIFO buffers.

8. An interface device according to claim 5, further comprising first control and status lines connected between each data buffer and the register set to communicate control and status signals to and from each data buffer.

9. An interface device according to claim 8, further comprising second control and status lines connected between each data buffer and the parallel interface to communicate control and status signals to and from each data buffer.

10. An interface device according to claim 1, wherein the UART standard is the 16550 standard.

11. A card comprising an interface device according to claim 1 integrated with the subsystem.

12. A card according to claim 11, wherein the subsystem includes a wireless interface for communicating with a third party data transceiver.

13. A system comprising a host, a subsystem and an interface device according to claim 1 connected between the host and subsystem.

14. A system according to claim 13, wherein the serial data communication channel and the auxiliary parallel data communication channel include wireless portions.

15. A system according to claim 13, wherein the serial data communication channel and the auxiliary parallel data communication channel are made exclusively of fixed links.

16. An interface device for enabling communications between a host and a subsystem, comprising:

(a) a register set comprising of a plurality of registers, wherein each of the plurality of registers is a standard UART register and wherein the register set is configurable to control host-subsystem communications;

(b) a host interface configurable to establish data communication with the host;

(c) a serial interface configurable to establish a bi-directional serial data communication channel to the subsystem under control of the register set; and

(d) a parallel interface configurable to establish an auxiliary parallel data communication channel to the subsystem, the parallel data communication channel being operable concurrently with the serial data communication channel, wherein the parallel interface operates under control of the register set.

17. A method of communicating data between a host and a subsystem, comprising:

(a) establishing a bi-directional serial data communication link with the subsystem under control of a register set, the register set comprising a plurality of registers wherein each of the plurality of registers is a standard UART register;

(b) establishing an auxiliary parallel data communication link with the subsystem also under control of the register set, the auxiliary parallel data communication link being operable concurrently with the serial data communication link; and

(c) transferring data over the auxiliary parallel data communication link to bypass the serial data communication link.