Generation of a secret quantity based on an identifier of an integrated circuit

• US 7,191,340 B2
• Filed: 10/10/2002
• Issued: 03/13/2007
• Est. Priority Date: 11/30/2001
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Wuidart, Luc, Bardouillet, Michel, Plaza, Laurent
• Primary Examiner(s): Moise; Emmanuel L.
• Assistant Examiner(s): Fields; Courtney D.
• Application Number:
  US10/269,098
• Publication Number:
  US 20030103629A1
• Time in Patent Office: 1,615 Days
• Field of Search: 713/189, 713/194, 380/265, 380/262, 380/263, 380/264
• US Class Current: 713/189
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics

Abstract

A method and a circuit for generating a secret quantity based on an identifier of an integrated circuit, in which a first digital word is generated from a physical parameter network, and this first word is submitted to at least one retroaction shift register, the output of the shift register forming the secret quantity.

Claims

1. A method for generating a secret quantity based on an identifier of an integrated circuit, including the steps of:

generating a first digital word from a physical parameter network; and

submitting this first word to at least one retroaction shift register, the output of said shift register forming said secret quantity.

2. The method of claim 1, comprising submitting the first word to several retroaction shift registers, and of selecting one of these registers to form the secret quantity.

3. The method of claim 2, wherein the selection is intended to be modified after a revocation of a preceding secret quantity.

4. The method of claim 1, wherein the shift register(s) are with a linear retroaction.

5. The method of claim 1, comprising selecting a shift register from among several ones by means of a selector.

6. A circuit for generating a secret quantity internal to an integrated circuit, including:

a generator of a first digital word specific to the integrated circuit chip based on a physical parameter network;

at least one retroaction shift register intended to receive as an input the first word and to provide said quantity; and

a selector of the drift sequence of the shift register, programmable by means of a counter.

8. The circuit of claim 6, wherein the selection performed by the selector is intended to be modified in case of a revocation of the secret datum.

10. The circuit of claim 6, wherein registers for storing the first word and the secret quantity are temporary storage elements, and wherein the circuit includes means for resetting these temporary storage elements after a predetermined duration.

11. The circuit of claim 10, wherein the storage elements are registers.

7. A circuit for generating a secret quantity internal to an integrated circuit, including:

a generator of a first digital word specific to the integrated circuit chip based on a physical parameter network;

several retroaction shift registers intended to receive as an input the first binary word; and

a selector of one of the shift registers to provide said secret quantity.

9. The circuit of claim 7, wherein the selector is formed of a multiplexer of selection of an input or output from among the inputs/outputs of the shift registers.

12. A circuit for generating a secret quantity in an integrated circuit, comprising:

a generator of a digital word based on a physical parameter network; and

at least one feedback shift register configured to receive the digital word and to provide the secret quantity.

13. A circuit as defined in claim 12, further comprising a selector configured to select a deriving sequence of the shift register.

14. A circuit as defined in claim 13, further comprising a counter configured to program the selector.

15. A circuit as defined in claim 12, wherein the at least one feedback shift register comprises a linear feedback shift register.

16. A circuit as defined in claim 12, wherein the at least one feedback shift register comprises a plurality of feedback shift registers, the circuit further comprising a selector configured to select one of the plurality of feedback shift registers to provide the secret quantity.

17. A circuit as defined in claim 16, wherein the selector comprises a multiplexer configured to select an input or an output from inputs and outputs of the plurality of shift registers.

18. A circuit as defined in claim 13, wherein the selection of the deriving sequence is modified after revocation of a preceding secret quantity.

19. A circuit as defined in claim 16, wherein the selected shift register is modified after revocation of a preceding secret quantity.

20. A circuit as defined in claim 12, further comprising a first register configured to store the digital word and a second register configured to store the secret quantity, the circuit further including means for resetting the first and second registers after a predetermined duration.

21. A circuit for generating a secret quantity in an integrated circuit, comprising:

a generator of a digital word based on a physical parameter network;

a plurality of feedback shift registers configured to receive the digital word; and

a selector configured to select one of the shift registers to provide the secret quantity.

22. A circuit as defined in claim 21, wherein the feedback shift registers comprise linear feedback shift registers.

23. A circuit as defined in claim 21, wherein the selected shift register is modified after revocation of a preceding secret quantity.

24. A circuit as defined in claim 21, wherein the selector comprises a multiplexer configured to select an input or an output of one of the shift registers.

25. A method for generating a secret quantity in an integrated circuit, comprising:

generating a digital word based on a physical parameter network; and

loading the digital word into at least one feedback shift register, an output of the at least one shift register constituting the secret quantity.

26. A method as defined in claim 25, further comprising selecting a deriving sequence of the at least one shift register.

27. A method as defined in claim 25, wherein loading the digital word comprises loading the digital word into a plurality of feedback shift registers and selecting one of the plurality of feedback shift registers to form the secret quantity.

28. A method as defined in claim 27, wherein selecting one of the plurality of feedback shift registers comprises modifying the selection after revocation of a preceding secret quantity.

29. A method as defined in claim 26, wherein selecting a deriving sequence comprises modifying the selection after revocation of a preceding secret quantity.