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Mechanism for processor power state aware distribution of lowest priority interrupt

  • US 7,191,349 B2
  • Filed: 12/26/2002
  • Issued: 03/13/2007
  • Est. Priority Date: 12/26/2002
  • Status: Active Grant
First Claim
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1. A method comprising:

  • receiving first power state information from a first component, said first power state information being information representing the power state of said first component, and second power state information from a second component, said second power state information being information representing the power state of said second component;

    receiving first task priority information from said first component and second task priority from said second component;

    receiving an interrupt request from a first device for servicing;

    evaluating power state and task priority information for said first and second components to determine which component should service said interrupt request;

    selecting either said first component or said second component to be a destination component to service said interrupt request based on said power state and task priority information; and

    communicating said interrupt request to said destination component.

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