Mechanism for processor power state aware distribution of lowest priority interrupt
First Claim
1. A method comprising:
- receiving first power state information from a first component, said first power state information being information representing the power state of said first component, and second power state information from a second component, said second power state information being information representing the power state of said second component;
receiving first task priority information from said first component and second task priority from said second component;
receiving an interrupt request from a first device for servicing;
evaluating power state and task priority information for said first and second components to determine which component should service said interrupt request;
selecting either said first component or said second component to be a destination component to service said interrupt request based on said power state and task priority information; and
communicating said interrupt request to said destination component.
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Accused Products
Abstract
A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
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Citations
36 Claims
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1. A method comprising:
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receiving first power state information from a first component, said first power state information being information representing the power state of said first component, and second power state information from a second component, said second power state information being information representing the power state of said second component; receiving first task priority information from said first component and second task priority from said second component; receiving an interrupt request from a first device for servicing; evaluating power state and task priority information for said first and second components to determine which component should service said interrupt request; selecting either said first component or said second component to be a destination component to service said interrupt request based on said power state and task priority information; and communicating said interrupt request to said destination component. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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interrupt handling logic coupled to a first set of signal lines to receive an interrupt request, said first set of signal lines coupled to one or more devices that can generate interrupt requests; a bus interface to interact with a bus coupled to a first component and a second component, wherein said interrupt handling logic is coupled to said first bus through said bus interface to receive power state information and task priority information for each of said first and second components, said power state information being information representing the power state of said components; evaluation logic coupled said interrupt handling logic, wherein when said interrupt handling logic receives said interrupt request, said evaluation logic is to evaluate power state and task priority information for said first and second components to determine which component should service said interrupt request; and selection logic coupled to said evaluation logic to select either said first component or said second component to be a destination component to service said interrupt request based on said power state and task priority information. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A system comprising:
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a bus; a first component and a second component coupled to said bus; one or more system devices that can generate interrupt requests, wherein said interrupt requests require service from either said first or second component; a chipset to handle said interrupt requests, said chipset coupled to said systems devices and to said first and second components, wherein said chipset is to receive power state information and task priority information for each of said first and second components, said power state information being information representing the power state of said first and second components, said chipset to evaluate said power state and task priority information when an interrupt request is received and to determine which component should service said interrupt request, and wherein said chipset selects either said first component or said second component to service said request based an said power state and task priority information. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A method comprising:
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receiving first power state information from a first component, said first power state information being information representing the power state of said first component, and second power state information from a second component, said second power state information being information representing the power state of said second component; assigning a first task priority value to said first component based on said first power state information; assigning a second task priority value to said second component based on said second power state information; receiving an interrupt request from a first device for servicing; evaluating task priority values for said first and second components to determine which component should service said interrupt request; selecting either said first component or said second component to be a destination component to service said interrupt request based on said task priority values; and communicating said interrupt request to said destination component. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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Specification