Method of forming a low capacitance semiconductor device and structure therefor

• US 7,192,814 B2
• Filed: 09/16/2004
• Issued: 03/20/2007
• Est. Priority Date: 09/16/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad
• Primary Examiner(s): Tran; Long K.
• Application Number:
  US10/942,060
• Publication Number:
  US 20060055025A1
• Time in Patent Office: 915 Days
• Field of Search: 438/197, 438/637, 438/157, 438/176, 438/283, 438/159, 257/341, 257/401, 257/E27.099, 257/E29.027
• US Class Current: 438/159
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Claims

1. A method of forming a semiconductor device comprising:

providing a substrate of a first conductivity type having a first surface;

forming a first source region and a second source region of the first conductivity type on at least a first portion of the first surface of the substrate wherein the second source region is spaced apart from the first source region;

forming a gate structure overlying the first surface of the substrate with a first end of the gate structure overlying an edge of the first source region and a second end of the gate structure overlying an edge of the second source region wherein a first surface of the gate structure is substantially parallel to the first surface of the substrate and faces away from the first surface of the substrate;

forming an opening in the gate structure and overlying a second portion of the substrate that is positioned in between the first source region and the second source region;

forming an insulator at least on sidewalls of the opening; and

forming a conductor within the opening and on the insulator wherein the conductor is not on the underlying substrate.

2. The method of claim 1 wherein forming the first source region and the second source region of the first conductivity type on at least the first portion of the first surface of the substrate wherein the second source region is spaced apart from the first source region includes forming a first body region of a second conductivity type on the first portion of the first surface of the substrate, forming a second body region of the second conductivity type on the first portion of the first surface of the substrate and spaced apart from the first body region, forming the first source region within the first body region with an edge of the first source region spaced apart from an edge of the first body region, and forming the second source region within the second body region with an edge of the second source region spaced apart from an edge of the second body region.

3. The method of claim 2 wherein forming the opening in the gate structure overlying the second portion of the substrate that is positioned in-between the first source region and the second source region includes forming the opening overlying the second portion of the substrate that is in-between the first body region and the second body region.

4. The method of claim 1 wherein forming the insulator at least on sidewalls of the opening includes forming a silicon dioxide insulator.

5. The method of claim 1 wherein forming the gate structure overlying the first surface of the substrate includes forming a gate conductor overlying the first surface of the substrate and forming an insulator layer on the gate conductor.

6. The method of claim 1 further including forming a source conductor on the gate structure and electrically contacting a portion of the first source region and a portion of the second source region.

7. The method of claim 1 wherein forming the conductor on the insulator includes forming the conductor to substantially not overlie the first surface of the gate structure.

8. The method of claim 1 wherein forming the conductor on the insulator within the opening includes forming polysilicon on the insulator that is within the opening and removing polysilicon that extends out of the opening.

9. The method of claim 1 wherein forming the conductor within the opening and on the insulator includes separating the conductor from the substrate by one of a portion of the insulator or a portion of another insulator that is a part of the gate structure.

10. A method of forming a semiconductor device comprising:

providing a semiconductor substrate of a first conductivity type having a surface;

forming a first body region of a second conductivity type on the surface of the semiconductor substrate;

forming a first region of the first conductivity type within the first body region and spaced apart from an edge of the first body region;

positioning a gate structure having a first portion overlying at least a portion of the first region, a second portion overlying a portion of the first body region, and a third portion overlying a first portion of the semiconductor substrate;

forming an opening in the gate structure wherein a sidewall of the opening forms a first sidewall of the gate structure;

forming an insulator on the first sidewall of the opening; and

forming a conductor abutting the insulator and overlying a second portion of the semiconductor substrate wherein the conductor does not overlie the first region of the first conductivity type.

11. The method of claim 10 wherein forming the conductor abutting the insulator and overlying the second portion of the semiconductor substrate includes forming doped polysilicon on the insulator within the opening.

12. The method of claim 10 further including forming a second body region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first body region;

forming a second region of the first conductivity type within the second body region and spaced apart from an edge of the second body region; and

forming a fourth portion of the gate structure overlying at least a portion of the second region, a fifth portion of the gate structure overlying a portion of the second body region, and a sixth portion overlying a third portion of the semiconductor substrate wherein the third portion of the semiconductor substrate is adjacent the second portion of the semiconductor substrate.

13. The method of claim 12 wherein forming the insulator, on the first sidewall of the gate structure further includes forming the insulator on a second sidewall of the gate structure wherein the second sidewall is a sidewall of the sixth portion of the gate structure.

14. The method of claim 10 wherein positioning the gate structure includes positioning the gate structure having a gate conductor layer and an insulator on the gate conductor layer.

15. The method of claim 14 wherein positioning the gate structure having the gate conductor layer and the insulator on the gate conductor layer includes positioning a silicon dioxide layer on the gate conductor layer and a silicon nitride layer on the silicon dioxide layer.

16. The method of claim 10 wherein forming the conductor abutting the insulator and overlying the second portion of the semiconductor substrate includes forming doped polysilicon abutting the insulator.

17. The method of claim 10 wherein forming the conductor abutting the insulator includes forming the conductor to not overlie the body region.