Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity

• US 7,192,881 B2
• Filed: 11/12/2004
• Issued: 03/20/2007
• Est. Priority Date: 11/28/2003
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kammler, Thorsten, Wieczorek, Karsten, Schwan, Christoph
• Primary Examiner(s): Pham, Thanhha S.
• Application Number:
  US10/987,466
• Publication Number:
  US 20050118769A1
• Time in Patent Office: 858 Days
• Field of Search: 438184-185, 438/230, 438/303, 438/595, 438/740, 438/738, 438743-744
• US Class Current: 438/740
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.

Claims

1. A method, comprising:

depositing a first silicon dioxide layer over a substrate comprising a line feature;

heat treating said substrate to densify said first silicon dioxide layer;

forming a first spacer layer over said densified first silicon dioxide layer;

anisotropically etching said first spacer layer while using said densified first silicon dioxide layer as an etch stop layer to form first sidewall spacers adjacent to said line feature, during said anisotropically etching said first spacer layer, an upper sidewall portion of said line feature being exposed through said first sidewall spacers; and

depositing a second silicon dioxide layer over said substrate, heat treating said substrate to density said second silicon dioxide layer, depositing a second spacer layer over said second silicon dioxide layer, and forming a second sidewall spacer adjacent to said first sidewall spacer by anisotropically etching said second spacer layer to expose said upper sidewall portion of said line feature.

2. The method of claim 1, wherein said first spacer layer comprises silicon nitride.

3. The method of claim 1, wherein heat treating said substrate is performed at a temperature of approximately 700°

C. and more.

4. The method of claim 1, further comprising implanting a dopant into said substrate while using said first sidewall spacer as an implantation mask.

5. The method of claim 1, further comprising implanting a dopant into said substrate while using said sidewall spacer and said second sidewall spacer as an implantation mask.

6. The method of claim 1, wherein a thickness of said first silicon dioxide layer is in the range of approximately 1–

10 nm.

7. The method of claim 1, further comprising implanting a dopant species into said substrate, wherein heat treating said substrate includes activating said dopant species and densifying said first silicon dioxide layer.

8. The method of claim 1, further comprising implanting a dopant species into said substrate adjacent to said line feature prior to heat treating said substrate to densify said first silicon dioxide layer.

9. A method, comprising:

depositing a first silicon dioxide layer over a substrate comprising a line feature;

forming a first spacer layer over said first silicon dioxide layer;

heat treating said substrate to densify said first silicon dioxide layer;

anisotropically etching said first spacer layer while using said densified first silicon dioxide layer as an etch stop layer to form first sidewall spacers adjacent to said line feature, during said anisotropically etching said first spacer layer, an upper sidewall portion of said line feature being exposed through said first sidewall spacers; and

depositing a second silicon dioxide layer over said substrate, heat treating said substrate to density said second silicon dioxide layer, depositing a second spacer layer over said second silicon dioxide layer, and forming a second sidewall spacer adjacent to said first sidewall spacer by anisotropically etching said second spacer layer to expose said upper sidewall portion of said line feature.

10. The method of claim 9, wherein said first spacer layer comprises silicon nitride.

11. The method of claim 9, wherein heat treating said substrate is performed at a temperature of approximately 700°

C. and more.

12. The method of claim 9, further comprising implanting a dopant into said substrate while using said first sidewall spacer as an implantation mask.

13. The method of claim 9, further comprising implanting a dopant into said substrate while using said first sidewall spacer and said second sidewall spacer as an implantation mask.

14. The method of claim 9, wherein a thickness of said first silicon dioxide layer is in the range of approximately 1–

10 nm.

15. The method of claim 9, further comprising implanting a dopant species into said substrate adjacent to said line feature prior to heat treating said substrate to densify said first silicon dioxide layer.