Three dimensional structure integrated circuit
DC CAFCFirst Claim
Patent Images
1. Circuitry comprising:
- a plurality of monolithic substrates having integrated circuits formed thereon and stacked in layers such that each layer comprises only one of the substrates, wherein at least one of the plurality of substrates is a substantially flexible substrate, and wherein a major portion of the monolithic substrate is removed; and
between adjacent substrates, a bonding layer bonding together the adjacent substrates, the bonding layer being formed by bonding first and second substantially planar surfaces having a bond-forming material throughout a majority of the surface area thereof.
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Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
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Citations
79 Claims
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1. Circuitry comprising:
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a plurality of monolithic substrates having integrated circuits formed thereon and stacked in layers such that each layer comprises only one of the substrates, wherein at least one of the plurality of substrates is a substantially flexible substrate, and wherein a major portion of the monolithic substrate is removed; and between adjacent substrates, a bonding layer bonding together the adjacent substrates, the bonding layer being formed by bonding first and second substantially planar surfaces having a bond-forming material throughout a majority of the surface area thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit structure comprising:
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a first substrate having a first surface; and a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, and wherein a major portion of the second substantially flexible monolithic monocrystalline semiconductor substrate is removed. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A stacked integrated circuit comprising:
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a plurality of integrated circuit substrates having formed on corresponding surfaces thereof complementary patterns of a material bondable using thermal diffusion bonding, wherein at least one of the plurality of substrates is a substantially flexible monolithic integrated circuit substrate, and wherein a major portion of the at least one substantially flexible monolithic integrated circuit substrate is removed; and a thermal diffusion bonded region between the complementary patterns. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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44. An integrated circuit structure comprising:
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a first substrate having a first surface; and a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, wherein at least one substrate of the first and second substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one substrate that has memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon. - View Dependent Claims (45)
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46. An integrated circuit structure comprising:
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a first substrate having a first surface; and a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface, wherein at least one substrate of the first and second substrates has reconfiguration circuitry. - View Dependent Claims (47)
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48. An integrated circuit structure comprising:
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a first substrate having a first surface; and a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface; a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell stores a data value and has circuitry for coupling that data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines; circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and a controller that determines if one of the plurality of memory cells is defective and alters the mapping to eliminate references to the one of the plurality of memory cells that is defective. - View Dependent Claims (49)
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50. An integrated circuit structure comprising:
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a first substrate having a first surface; and a second substrate bonded to the first surface of the first substrate to form conductive paths between the first substrate and the second substrate wherein the second substrate is a substantially flexible monolithic monocrystalline semiconductor substrate having active circuitry formed thereon, wherein no other substrates are bonded to the first surface; at least one controller substrate having logic circuitry formed thereon; at least one memory substrate having memory circuitry formed thereon; a plurality of data lines and a plurality of gate lines on each memory substrate; an array of memory cells on each memory substrate, each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting of one of the plurality of gate lines; a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates to receive address assignments for at least one of the plurality of gate lines and wherein the address assignments for determining which of the plurality of gate lines is selected for each programmed address assignment; and controller substrate logic that determines if one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines. - View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. An integrated circuit structure comprising:
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a plurality of semiconductor dice, each die having an integrated circuit formed thereon, said dice being stacked in layers, wherein at least one of the plurality of dice is substantially flexible, and wherein at least one of the plurality of dice has at least one of polycrystalline active circuitry formed thereon, reconfiguration circuitry formed thereon, and passive circuitry formed thereon; and between adjacent dice, a bonding layer bonding together the adjacent dice, the bonding layer bonding first and second substantially planar adjacent surfaces of the adjacent dice, with at least one or more portions of the bonding layer being located other than at the edges of the adjacent dice. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69)
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70. An integrated circuit structure comprising:
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a substrate having a first surface; and a semiconductor die having an integrated circuit formed thereon bonded to the first surface of the substrate with conductive paths between the substrate and the die wherein the die is substantially flexible, wherein the semiconductor die is attached to the first surface of the substrate by one or more bonds including one bond located other than at the edges of the semiconductor die, and wherein at least one of the substrate and die has at least one of polycrystalline active circuitry formed thereon, reconfiguration circuitry formed thereon, and passive circuitry formed thereon. - View Dependent Claims (71, 72, 73, 74, 75, 76, 77, 78, 79)
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Specification