Non-planar MOS structure with a strained channel region

• US 7,193,279 B2
• Filed: 01/18/2005
• Issued: 03/20/2007
• Est. Priority Date: 01/18/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Doyle, Brian S., Datta, Suman, Chau, Robert
• Primary Examiner(s): Soward; Ida M.
• Application Number:
  US11/039,197
• Publication Number:
  US 20060157687A1
• Time in Patent Office: 791 Days
• Field of Search: 257/19, 257/288, 257/328, 257/331, 257/401, 257/618, 257/623
• US Class Current: 257/401
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

Claims

1. A non-planar transistor comprising:

a silicon germanium body with a top and two sidewalls formed on a substrate and electrically isolated from the substrate;

a doped strained silicon film formed on the sidewalls of the silicon germanium body;

a gate dielectric formed on the strained silicon film;

a gate formed on the gate dielectric; and

a source and a drain formed in the strained silicon.

2. The non-planar transistor of claim 1, the silicon germanium body comprising a germanium concentration of approximately between 5% and 80%.

3. The non-planar transistor of claim 2, the silicon germanium body comprising a germanium concentration of approximately 150%.

4. The non-planar transistor of claim 1, the gate dielectric comprising a material selected from the group consisting of silicon dioxide, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantanate, and lead zinc niobate.

5. The non-planar transistor of claim 1, the gate comprising a material selected from the group consisting of polysilicon, metal, and a combination thereof.

6. The non-planar transistor of claim 1 wherein the silicon germanium body has a substantially rectangular cross section and the doped strained silicon film is formed on a the top and both sidewalls of the silicon germanium body.

7. The non-planar transistor of claim 1 wherein the silicon germanium body has a substantially trapezoidal cross section and the doped strained silicon film is formed on a the top and both sidewalls of the silicon germanium body.

8. The non-planar transistor of claim 1 wherein the doped strained silicon film has a thickness of approximately between 2 nanometers and 10 nanometers.

9. The non-planar transistor of claim 8 wherein the doped strained silicon film has a thickness of approximately between 4 nanometers and 5 nanometers.

10. A tri-gate transistor comprising:

a silicon germanium fin formed on an insulator, the silicon germanium fin including a top surface and two sidewall surfaces;

a doped strained silicon film formed on the top surface and two sidewall surfaces of the silicon germanium fin;

a gate dielectric formed on the strained silicon film;

a gate formed on the gate dielectric wherein the gate extends over the top surface of the silicon germanium fin; and

a source and a drain formed in the strained silicon film.

11. The tri-gate transistor of claim 10, the silicon germanium fin comprising a germanium concentration of approximately between 5% and 80%.

12. The tri-gate transistor of claim 11, the silicon germanium fin comprising a germanium concentration of approximately 15%.

13. The tri-gate transistor of claim 10 wherein the strained silicon film has a thickness of approximately between 2 nanometers and 10 nanometers.

14. The tri-gate transistor of claim 13 wherein the strained silicon film has a thickness of approximately between 4 nanometers and 5 nanometers.

15. The tri-gate transistor of claim 10 wherein the silicon germanium fin is doped.

16. The tri-gate transistor of claim 15 wherein the silicon germanium fin is doped with a p-dopant concentration of between approximately undoped and 6*10.sup.19 cm.sup.-3.

17. The tri-gate transistor of claim 10 wherein the strained silicon is doped with a p-dopant concentration of between approximately undoped and 6*10.sup.19 cm.sup.-3.

18. A non-planar transistor comprising:

a silicon germanium body with a top and two sidewalls formed on a substrate and electrically isolated from the substrate, the silicon germanium body comprising a silicon germanium layer interdiffused with a silicon layer such that the silicon layer has a substantially uniform germanium concentration;

a strained silicon film formed on the sidewalls of the silicon germanium body;

a gate dielectric formed on the doped strained silicon film;

a gate formed on the gate dielectric; and

a source and a drain formed in the doped strained silicon film.

19. The non-planar transistor of claim 18 wherein the silicon germanium body has a substantially rectangular cross section and the strained silicon film is formed on the top and both sidewalls of the silicon germanium body.

20. The non-planar transistor of claim 18 wherein the silicon germanium body is doped.

21. The non-planar transistor of claim 20 wherein the silicon germanium body is doped with a p-dopant concentration of between approximately undoped and 6*10.sup.19 cm.sup.-3.

22. The non-planar transistor of claim 18 wherein the strained silicon film is doped.

23. The non-planar transistor of claim 22 wherein the strained silicon film is doped with a p-dopant concentration of between approximately undoped and 6*10.sup.19 cm.sup.-3.