Castellation wafer level packaging of integrated circuit chips

• US 7,193,312 B2
• Filed: 09/07/2005
• Issued: 03/20/2007
• Est. Priority Date: 08/28/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Neo, Yong Loo, Boon, Suan Jeung, Zhou, Wei, Low, Siu Waf, Chua, Swee Kwang, Chia, Yong Poo, Eng, Meow Koon, Huang, Shuang Wu
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US11/222,365
• Publication Number:
  US 20060001143A1
• Time in Patent Office: 559 Days
• Field of Search: 257/690, 257/730, 257/678
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Claims

1. Castellation wafer level packages for packaging integrated circuit chips, said packages comprising:

an integrated circuit chip depositing on a wafer;

a castellation contact deposited on the wafer, wherein the castellation contact is large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste, wherein the castellation contact is substantially encapsulated by an encapsulant such that a top surface of the castellation contact is left exposed, and wherein the wafer, castellation contact, and encapsulant are cut to expose a surface of the castellation contact; and

an active circuit area contact coupled to an active circuit area of the integrated circuit chip and the top surface of the castellation contact.

2. The packages of claim 1 wherein the castellation contact is a castellation block.

3. The packages of claim 1 further comprising an input/output pad coupled to the castellation contact.

4. The package of claim 1 wherein the integrated circuit chip is adapted to be written to and read from.

5. The package of claim 4 wherein information is written to or read from the integrated circuit chip when the chip is activated.

6. The package of claim 5 wherein the integrated circuit chip is activated in response to an activation signal.

7. The package of claim 6 wherein the activation signal is applied to the castellation contact.

8. The package of claim 6 wherein the activation signal is a “

code”

or “

key”

signal.

9. The package of claim 6 wherein there is more than one castellation contact coupled to the integrated circuit chip, wherein the activation signal is applied to more than one castellation contact.

10. The package of claim 6 wherein the activation signal is a signal selected from the group consisting of a binary code, an analog signal, and combinations thereof.

11. The package of claim 1 wherein the integrated circuit chip is coupled to a device that can write information to and read information from the integrated circuit chip.

12. The package of claim 11 wherein the device is a motherboard.

13. The package of claim 11 wherein the device is coupled to the integrated circuit chip via a motherboard.