VPA logic circuits

• US 7,193,432 B1
• Filed: 06/30/2004
• Issued: 03/20/2007
• Est. Priority Date: 02/14/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Schmit, Herman
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Crawford, Jason
• Application Number:
  US10/882,579
• Time in Patent Office: 993 Days
• Field of Search: 326 38- 41, 326/47, 716/16, 257/774
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

Claims

1. An integrated circuit (IC) comprising:

a) a first logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set;

b) a second circuit communicatively coupled to the first logic circuit, the second circuit for supplying configuration data sets to the first logic circuit, the second circuit having a first set of input terminals;

c) a second set of input terminals for carrying data, wherein a plurality of the second set of input terminals overlap a plurality of the first set of input terminals; and

d) a set of vias, wherein each via connects an input terminal in the first set with an input terminal in the second set;

wherein, through the set of vias, the first set of input terminals receives, from the second set of input terminals, data that serves as at least one configuration data set.

2. The IC of claim 1, wherein the second circuit is for supplying configuration data sets to the first logic circuit at a particular rate for at least a duration of time.

3. The IC of claim 1, wherein the second circuit receives configuration data through the via connections between the first and second input terminal sets.

4. The IC of claim 3, wherein the second set of input terminals is for carrying 0 and 1 data.

5. The IC of claim 1, wherein the second circuit receives a control signal that directs the second circuit to supply configuration data sets to the first logic circuit at a particular rate.

6. The IC of claim 5 further comprising a sub-cycle signal generator that generates the control signal.

7. The IC of claim 6, wherein the sub-cycle control signal is a clock signal.

8. The IC of claim 6, wherein the sub-cycle control signal has a value that can change at the sub-cycle rate.

9. The IC of claim 1 further comprising:

a plurality of configurable logic circuits, each configurable logic circuit comprising;

1) a first logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set;

2) a second circuit communicatively coupled to the first logic circuit, the second circuit for supplying configuration data sets to the first logic circuit, the second circuit having a first set of input terminals;

3) a second set of input terminals for carrying data, wherein a plurality of the second set of input terminals overlap a plurality of the first set of input terminals; and

4) a set of vias, wherein each via connects an input terminal in the first set with an input terminal in the second set;

wherein, through the set of vias, the first set of input terminals receives, from the second set of input terminals, data that serves as at least one configuration data set.

10. A configurable logic circuit comprising:

a) a first logic circuit for receiving configuration data sets;

b) a second circuit communicatively coupled to the first logic circuit, the second circuit for supplying configuration data sets to the first logic circuit, the second circuit having a first set of input terminals;

c) a second set of input terminals for carrying data, wherein a plurality of the second set of input terminals overlap a plurality of the first set of input terminals;

d) a set of vias, wherein each via connects an input terminal in the first set with an input terminal in the second set;

wherein, through the set of vias, the first set of input terminals receives, from the second set of input terminals, data that serves as at least one configuration data set.

11. The configurable logic circuit of claim 10, wherein the first logic circuit is for performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set.

12. The configurable logic circuit of claim 11, wherein the second circuit is for supplying configuration data sets to the first logic circuit at a particular rate for at least a duration of time.

13. The configurable logic circuit of claim 11, wherein the second circuit receives configuration data through the via connections between the first and second input terminal sets.

14. The configurable logic circuit of claim 13, wherein the second set of input terminals are for carrying 0 and 1 data.

15. The configurable logic circuit of claim 11, wherein the second circuit receives a control signal that directs the second circuit to supply configuration data sets to the first logic circuit at a particular rate.

16. The configurable logic circuit of claim 15 further comprising a sub-cycle signal generator that generates the control signal.

17. The configurable logic circuit of claim 16, wherein the sub-cycle control signal is a clock signal.

18. The configurable logic circuit of claim 16, wherein the sub-cycle control signal has a value that can change at the sub-cycle rate.

19. The configurable logic circuit of claim 10, wherein the configurable logic circuit has inputs for receiving input data and a configuration signal for directing the configurable logic circuit to select different sets of the configuration data, wherein each configuration data set determines a particular function that the configurable logic circuit performs on the input data to produce output data.

20. The configurable logic circuit of claim 19, wherein the second circuit receives the configuration signal, and based on the configuration signal, supplies different configuration data sets to the first logic circuit.

21. The configurable logic circuit of claim 20, wherein the first logic circuit receives the input data, and based on each configuration data set received from the second circuit, performs a particular function on the input data.

22. The configurable logic circuit of claim 19, wherein the second set of input terminals carries a portion of the configuration signal.

23. The configurable logic circuit of claim 22, wherein the second circuit receives a portion of the configuration signal.

24. The configurable logic circuit of claim 23, wherein the first logic circuit receives the input data, and based on each configuration data set received from the second circuit, performs a particular function on the input data.

25. The configurable logic circuit of claim 23, wherein the second circuit receives a portion of the input signal.

26. The configurable logic circuit of claim 25, wherein the first logic circuit receives a portion of the configuration signal.

27. The configurable logic circuit of claim 26, wherein the first logic circuit further receives a portion of the input signal.

28. The configurable logic circuit of claim 19, wherein the second set of input terminals carries a portion of the input signal.

29. The configurable logic circuit of claim 28, wherein the second circuit receives a portion of the configuration signal.

30. The configurable logic circuit of claim 29, wherein the first logic circuit receives a portion of input data.

31. The configurable logic circuit of claim 30, wherein the first logic circuit receives a portion of configuration signal.

32. An integrated circuit (IC) comprising:

a) a first logic circuit for receiving configuration data sets and for performing at least two different functions based on at least two different configuration data sets;

b) a second switching circuit communicatively coupled to the first logic circuit, the second circuit for switchably supplying configuration data sets to the first logic circuit, the second circuit having a first set of input terminals;

c) a second set of input terminals for carrying data, wherein a plurality of the second set of input terminals overlap a plurality of the first set of input terminals; and

d) a plurality of vias each connecting an input terminal in the first set with an input terminal in the second set.