Programmable logic block having lookup table with partial output signal driving carry multiplexer

• US 7,193,433 B1
• Filed: 06/14/2005
• Issued: 03/20/2007
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Young, Steven P.
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): Crawford; Jason
• Application Number:
  US11/151,988
• Time in Patent Office: 644 Days
• Field of Search: 326 38- 39, 326/41, 326/47, 708/232, 708/235
• US Class Current: 326/38
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT. In one embodiment, a first LUT output terminal provides a signal that depends upon fewer than all of the LUT data input signals, and the second LUT output terminal provides a signal that depends upon all of the LUT data input signals. In another embodiment, the first output signal depends upon X of the input signals and the second output signal depends upon Y of the input signals, X and Y being positive integers, X being less than Y. The first LUT output terminal drives a data input terminal, and the second LUT output terminal drives a select input terminal, of the carry chain multiplexer.

Claims

1. A programmable logic block, comprising:

a lookup table (LUT) having a plurality of input terminals providing a plurality of LUT data input signals, and further having first and second output terminals, wherein the first output terminal provides a first output signal having a first value that depends upon fewer than all of the LUT data input signals and the second output terminal provides a second output signal having a second value that depends upon all of the LUT data input signals; and

a carry multiplexer having a first data input terminal coupled to the first output terminal of the LUT, a second data input terminal coupled to an output terminal of a carry multiplexer included in a first adjacent programmable logic block, an output terminal coupled to a data input terminal of a carry multiplexer included in a second adjacent programmable logic block, and a select terminal coupled to the second output terminal of the LUT.

2. The programmable logic block of claim 1, further comprising an additional multiplexer coupled between the first output terminal of the LUT and the first data input terminal of the carry multiplexer, the additional multiplexer comprising:

a first data input terminal coupled to the first output terminal of the LUT;

a second data input terminal coupled to a direct input terminal of the programmable logic block; and

an output terminal coupled to the first data input terminal of the carry multiplexer.

3. The programmable logic block of claim 1, further comprising a logic block output terminal programmably coupled to the first output terminal of the LUT and the output terminal of the carry multiplexer.

4. The programmable logic block of claim 3, wherein the logic block output terminal is further programmably coupled to the second output terminal of the LUT.

5. An integrated circuit, comprising:

an interconnect structure; and

a plurality of programmable logic blocks coupled to the interconnect structure, each programmable logic block comprising;

a lookup table (LUT) having a plurality of input terminals providing a plurality of LUT data input signals, and further having first and second output terminals, wherein the first output terminal provides a first output signal having a first value that depends upon fewer than all of the LUT data input signals and the second output terminal provides a second output signal having a second value that depends upon all of the LUT data input signals; and

a carry multiplexer having a first data input terminal coupled to the first output terminal of the LUT, a second data input terminal coupled to an output terminal of a carry multiplexer included in a first adjacent programmable logic block, an output terminal coupled to a data input terminal of a carry multiplexer included in a second adjacent programmable logic block, and a select terminal coupled to the second output terminal of the LUT.

6. The integrated circuit of claim 5, wherein each programmable logic block further comprises an additional multiplexer coupled between the first output terminal of the LUT and the first data input terminal of the carry multiplexer, the additional multiplexer comprising:

a first data input terminal coupled to the first output terminal of the LUT;

a second data input terminal coupled to a direct input terminal of the programmable logic block; and

an output terminal coupled to the first data input terminal of the carry multiplexer.

7. The integrated circuit of claim 5, wherein each programmable logic block further comprises a logic block output terminal programmably coupling the first output terminal of the LUT and the output terminal of the carry multiplexer to the interconnect structure.

8. The integrated circuit of claim 7, wherein the logic block output terminal is further programmably coupled to the second output terminal of the LUT.

9. The integrated circuit of claim 5, wherein the integrated circuit comprises a programmable logic device (PLD).

10. The integrated circuit of claim 9, wherein the integrated circuit comprises a field programmable gate array (FPGA).

11. An integrated circuit, comprising:

an interconnect structure; and

a plurality of programmable logic blocks coupled to the interconnect structure, each programmable logic block comprising;

a lookup table (LUT) having a plurality of input terminals providing a plurality of LUT data input signals, and further having first and second output terminals, wherein the first output terminal provides a first output signal having a first value that depends upon X of the LUT data input signals and the second output terminal provides a second output signal having a second value that depends upon Y of the LUT data input signals, X and Y being positive integers and X being less than Y; and

a carry multiplexer having a first data input terminal coupled to the first output terminal of the LUT, a second data input terminal coupled to an output terminal of a carry multiplexer included in a first adjacent programmable logic block, an output terminal coupled to a data input terminal of a carry multiplexer included in a second adjacent programmable logic block, and a select terminal coupled to the second output terminal of the LUT.

12. The integrated circuit of claim 11, wherein each programmable logic block further comprises an additional multiplexer coupled between the first output terminal of the LUT and the first data input terminal of the carry multiplexer, the additional multiplexer comprising:

a first data input terminal coupled to the first output terminal of the LUT;

a second data input terminal coupled to a direct input terminal of the programmable logic block; and

an output terminal coupled to the first data input terminal of the carry multiplexer.

13. The integrated circuit of claim 11, wherein each programmable logic block further comprises a logic block output terminal programmably coupling the first output terminal of the LUT and the output terminal of the carry multiplexer to the interconnect structure.

14. The integrated circuit of claim 13, wherein the logic block output terminal is further programmably coupled to the second output terminal of the LUT.

15. The integrated circuit of claim 11, wherein the integrated circuit comprises a programmable logic device (PLD).

16. The integrated circuit of claim 15, wherein the integrated circuit comprises a field programmable gate array (FPGA).