Configurable integrated circuit with offset connection

• US 7,193,438 B1
• Filed: 06/30/2004
• Issued: 03/20/2007
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Chang, Daniel D.
• Application Number:
  US10/882,713
• Time in Patent Office: 993 Days
• Field of Search: 326/38, 326/39, 326/41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Claims

1. An integrated circuit (“

IC”

) comprising;

a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns;

a plurality of direct offset connections, wherein each particular direct offset connection connects two configurable nodes that are neither in the same column nor in the same row in the array and which are separated by at least three rows or at least three columns;

and wherein said plurality of direct offset connections does not include any intervening routing circuits.

2. The integrated circuit of claim 1, wherein a subset of said plurality of direct offset connections do not include any intervening circuits.

3. The integrated circuit of claim 1, wherein each of said plurality of direct offset connections includes a set of wire segments and a set of vias.

4. The integrated circuit of claim 3, wherein none of the plurality of direct offset connections include intervening circuits.

5. The integrated circuit of claim 3, wherein a subset of said plurality of direct offset connections includes intervening circuits.

6. The integrated circuit of claim 5, wherein the intervening circuits are buffer circuits.

7. The integrated circuit of claim 1, wherein each of the configurable nodes is a configurable circuit for configurably performing a set of operations.

8. The integrated circuit of claim 1, wherein each of a plurality of configurable nodes includes more than one configurable circuit.

9. The integrated circuit of claim 1, wherein the configurable nodes in the array are similar.

10. The integrated circuit of claim 9, wherein the configurable nodes in the array have the same set of circuit elements and the same wiring between the circuit elements.

11. The integrated circuit of claim 1, wherein each of a plurality of configurable nodes that is connected to another configurable node by a direct offset connection is also connected to at least one additional configurable node that is in the same column or same row as the configurable node.

12. The integrated circuit of claim 1, wherein a plurality of pairs of configurable nodes are neighboring offset node pairs, wherein a neighboring offset node pair is a pair of configurable nodes that includes two nodes that are one row and one column apart from each other.

13. The integrated circuit of claim 12 further comprising a plurality of direct connections between pairs of neighboring nodes that are in the same row or column.

14. The integrated circuit of claim 1, wherein each of a plurality of offset pairs of nodes is a pair of nodes that are separated in the array by at least two rows or two columns.

15. The integrated circuit of claim 13, wherein each of a subset of said plurality of offset pairs of nodes is a pair of nodes that are separated in the array by at least two rows and one column, or at least two columns and one row.

16. The integrated circuit of claim 1, wherein the array includes more than 256 configurable nodes.

17. An integrated circuit (“

IC”

) comprising;

a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns;

a plurality of direct long offset connections, wherein each particular direct long offset connection connects two offset nodes that are separated in the array by at least four rows and one column, or at least four columns and one row; and

wherein said plurality of direct long offset connections does not include any intervening routing circuits.

18. The integrated circuit of claim 17, wherein each of the configurable nodes is a configurable circuit for configurably performing a set of operations.

19. The integrated circuit of claim 17, wherein the configurable nodes in the array have the same set of circuit elements and the same wiring between the circuit elements.

20. The integrated circuit of claim 17, wherein each of the configurable nodes is a configurable interconnect circuit.

21. The integrated circuit of claim 20, wherein each of the configurable nodes is a configurable logic circuit.