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Integrated circuit with tamper detection circuit

  • US 7,193,482 B2
  • Filed: 10/29/2004
  • Issued: 03/20/2007
  • Est. Priority Date: 07/15/1997
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit having a tamper detection circuit including:

  • a noise generator circuit having a pseudo-random bit generator clocked at high speed relative to the general circuits of an integrated circuit;

    a first line connected to the noise generator circuit; and

    a second line connected to the noise generator circuit by an inverter;

    wherein operation of one or more general circuits of the integrated circuit is dependent upon a logical combination of signals on the first line and the second line.

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