Liquid crystal display device with color filter in direct contact with drain and source electrode of TFT
First Claim
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1. A liquid crystal display (LCD) device, comprising:
- a thin film transistor (TFT) formed on a substrate, the TFT having a gate, a source and a drain;
a semiconductor layer aligned with the gate and having end portions extending beyond outside edges of the gate;
a color filter layer on the TFT, and in direct contact with the source and the drain, wherein said contact is only at a portion where said color filter layer is overlapping only edge portions of the source and drain so as to prevent light leakage and improve an aperture ratio;
a planarization layer formed over the TFT and the color filter layer, anda pixel electrode formed above the planarization layer and the color filter layer to be in electrical contact with the drain through a contact hole formed in the planarization layer where the color filter layer is not formed,wherein the source and drain are spaced apart from each other and overlap both end portions of the semiconductor layer, andwherein the contact hole is formed in the planarization layer at a position corresponding to the end portion of the semiconductor layer above the drain.
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Abstract
A liquid crystal display (LCD) device having a color filter on a thin film transistor (TFT) structure (COT structure). The color filter layers are formed on the same substrate as the TFT to be in direct contact with the source and drain electrodes without any intermediaries therebetween. In particular, there is no need for a passivation layer between the TFT and the color filter layers. Preferred embodiments include a back etched type TFT that does not require a light shielding layer, an etch-stopped type TFT having an etch stop layer, and a coplanar type TFT having a light shielding layer below the gate electrode of the TFT.
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8 Claims
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1. A liquid crystal display (LCD) device, comprising:
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a thin film transistor (TFT) formed on a substrate, the TFT having a gate, a source and a drain; a semiconductor layer aligned with the gate and having end portions extending beyond outside edges of the gate; a color filter layer on the TFT, and in direct contact with the source and the drain, wherein said contact is only at a portion where said color filter layer is overlapping only edge portions of the source and drain so as to prevent light leakage and improve an aperture ratio; a planarization layer formed over the TFT and the color filter layer, and a pixel electrode formed above the planarization layer and the color filter layer to be in electrical contact with the drain through a contact hole formed in the planarization layer where the color filter layer is not formed, wherein the source and drain are spaced apart from each other and overlap both end portions of the semiconductor layer, and wherein the contact hole is formed in the planarization layer at a position corresponding to the end portion of the semiconductor layer above the drain. - View Dependent Claims (2, 3, 4)
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5. A method of manufacturing a liquid crystal display (LCD) device, comprising:
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forming a thin film transistor (TFT) on a substrate, the TFT having a gate, a source and a drain; forming a semiconductor layer aligned with the pate and having end portions extending beyond outside edaes of the pate; forming a color filter layer on the TFT, in direct contact with the source and the drain, wherein said contact is only at a portion where said color filter layer is overlapping only edge portions of the source and drain so as to prevent light leakage and improve an aperture ratio; forming a planarization layer over the TFT and the color filter layer; and forming a pixel electrode above the planarization layer and the color filter layer to be in electrical contact with the drain through a contact hole formed in the planarization layer where the color filter layer is not formed, wherein the source and drain are formed to be spaced apart from each other and overlap both end portions of the semiconductor layer, and wherein the contact hole is formed in the planarization layer at a position corresponding to the end portion of the semiconductor aver above the drain. - View Dependent Claims (6, 7, 8)
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Specification