Compensation currents in non-volatile memory read operations

• US 7,193,898 B2
• Filed: 06/20/2005
• Issued: 03/20/2007
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US11/157,033
• Publication Number:
  US 20060285391A1
• Time in Patent Office: 638 Days
• Field of Search: 365/185.22, 365/185.17, 365/189.01, 365/189.04, 365/189.07
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.

Claims

1. A method of reading data from non-volatile storage, comprising:

reading a first non-volatile storage element of a first group of non-volatile storage elements to determine whether said first non-volatile storage element is programmed to a first programmed state;

providing an initialization voltage to a bit line of said first group if said first non-volatile storage element is determined to be in said first programmed state, said providing resulting in a first current in a bit line of a second group of non-volatile storage elements; and

reading a second non-volatile storage element of said second group while said first current is in said bit line of said second group of non-volatile storage elements if said first non-volatile storage element is programmed to said first programmed state.

2. The method of claim 1, wherein said step of reading said first non-volatile storage element comprises:

determining whether a threshold voltage of said first non-volatile storage element is at or above a first reference read level corresponding to said first programmed state.

3. The method of claim 1, wherein said step of reading said first non-volatile storage element comprises:

determining whether a conduction current of said first non-volatile storage is at or above a first breakpoint level corresponding to said first programmed state.

4. The method of claim 1, wherein:

said step of providing said initialization voltage induces said first current in said bit line of said second group by creating a difference in voltage between said bit line of said first group and said bit line of said second group, said first current flows from said bit line of said second group to said bit line of said first group as a result of capacitive coupling.

5. The method of claim 1, wherein said step of providing includes:

grounding said first bit line of said first group of non-volatile storage elements.

6. The method of claim 1, wherein:

said first current in said second bit line increases an apparent conduction current of said second non-volatile storage element.

7. The method of claim 1, wherein said step of reading said second non-volatile storage element includes:

sensing a conduction current of said second non-volatile storage element during a first sampling period, said first current increases an apparent value of said conduction current.

8. The method of claim 7, further comprising:

reading said second non-volatile storage element without said first current in said bit line of said second group of non-volatile storage elements if said first non-volatile storage element is not programmed to said first programmed state.

9. The method of claim 8, wherein:

said reading without said second current in said bit line of said second group is performed during a second sampling period, said first sampling period is before said second sampling period.

10. The method of claim 1, wherein:

said step of reading said second non-volatile storage element includes sensing whether a voltage level at a sensing circuit for said second group of non-volatile storage elements drops below a predetermined level corresponding to a second programmed state within a first period of time; and

said first current in said bit line of said second group increases a rate at which said voltage level at said sensing circuit drops during said first period of time.

11. The method of claim 1, wherein:

said first group of non-volatile storage elements is a first NAND string; and

said second group of non-volatile storage elements is a second NAND string adjacent to said first NAND string.

12. The method of claim 11, wherein:

said first non-volatile storage element is coupled to a first word line; and

said second non-volatile storage element is coupled to said first word line.

13. The method of claim 11, wherein:

said first non-volatile storage element is coupled to a first word line; and

said second non-volatile storage element is coupled to a second word line adjacent to said first word line.

14. The method of claim 1, wherein:

said first programmed state is one of a plurality of states to which said first group of non-volatile storage elements can be programmed; and

said first programmed state includes a highest threshold voltage range of said plurality of states.

15. The method of claim 1, wherein:

said step or reading includes determining whether said first non-volatile storage element is programmed to said first programmed state or at least one other programmed state; and

said step of providing includes providing said initialization voltage to said bit line of said first group if said first non-volatile storage element is programmed to said first programmed state or said at least one other programmed state.

16. The method of claim 1, wherein:

said first programmed state is one of a plurality of states to which said first group of non-volatile storage elements can be programmed;

said initialization voltage is a first initialization voltage;

said step of reading includes determining whether said first non-volatile storage element is programmed to said first programmed state or at least one other programmed state of said plurality of states; and

said method further comprises providing a second initialization voltage to said bit line of said first group of non-volatile storage elements if said first non-volatile storage element is programmed to said at least one other programmed state.

17. The method of claim 16, wherein:

a threshold voltage range of said first programmed state is at a higher level than a threshold voltage of said at least one other programmed state; and

said first initialization voltage is lower than said second initialization voltage.

18. The method of claim 1, wherein:

said step of reading said second non-volatile storage element is a second reading of said second non-volatile storage element to determine whether said second non-volatile storage element is programmed to a second programmed state; and

said step of reading said first non-volatile storage element includes a first reading of said second non-volatile storage element to determine whether said second non-volatile storage element is programmed to said first programmed state.

19. The method of claim 1, wherein:

said first non-volatile storage element and said second non-volatile storage element are part of a set of non-volatile storage elements;

said set of non-volatile storage elements includes a single page of data; and

non-volatile storage elements of said set are connected to a first word line and consecutive bit lines.

20. The method of claim 19, wherein:

said set of non-volatile storage elements are read by simultaneously reading said consecutive bit lines;

said reading said first non-volatile storage element is part of a first read of said set of non-volatile storage elements using a first reference read voltage associated with said first programmed state; and

said reading said second non-volatile storage element is part of a second read of said set of non-volatile storage elements using a second reference read voltage associated with a second programmed state.

21. The method of claim 1, wherein:

said first non-volatile storage element and said second non-volatile storage element are part of a set of non-volatile storage elements, said first non-volatile storage element is part of a first subset of said set and said second non-volatile storage element is part of a second subset of said set;

non-volatile storage elements of said set are connected to a first word line and consecutive bit lines;

said set of non-volatile storage elements includes a single page of data;

non-volatile storage elements of said first subset of non-volatile storage elements are coupled to a first subset of said consecutive bit lines that includes every other bit line;

non-volatile storage elements of said second subset of non-volatile storage elements are coupled to a second subset of said consecutive bit lines that includes every other bit line; and

said first subset of non-volatile storage elements are read and programmed at a different time than said second subset of non-volatile storage elements.

22. The method of claim 1, wherein:

said first non-volatile storage element and said second non-volatile storage element are part of a set of non-volatile storage elements;

non-volatile storage elements of said set are connected to a first word line and consecutive bit lines;

said set of non-volatile storage elements includes a first page of data and a second page of data; and

said first and second non-volatile storage elements each store a portion of said first page of data and a portion of said second page of data.

23. The method of claim 22, wherein:

said set of non-volatile storage elements are read by simultaneously reading said consecutive bit lines;

said reading said first non-volatile storage element is part of a first read of said set of non-volatile storage elements using a first reference read voltage associated with said first programmed state; and

said reading said second non-volatile storage element is part of a second read of said set of non-volatile storage elements using a second reference read voltage associated with a second programmed state.

24. The method of claim 1, wherein:

said first non-volatile storage element and said second non-volatile storage element are part of a set of non-volatile storage elements, said first non-volatile storage element is part of a first subset of said set and said second non-volatile storage element is part of a second subset of said set;

non-volatile storage elements of said set are connected to a first word line and consecutive bit lines;

said set of non-volatile storage elements includes a first page of data and a second page of data;

said first and second non-volatile storage elements each store a portion of said first page of data and a portion of said second page of data;

non-volatile storage elements of said first subset of non-volatile storage elements are coupled to a first subset of said consecutive bit lines that includes every other bit line; and

non-volatile storage elements of said second subset of non-volatile storage elements are coupled to a second subset of said consecutive bit lines that includes every other bit line.

25. The method of claim 1, further comprising:

reading a third non-volatile storage element of a third group of non-volatile storage elements to determine whether said third non-volatile storage element is programmed to said first programmed state; and

providing an initialization voltage to a bit line of said third group if said third non-volatile storage element is determined to be in said first programmed state, said providing resulting in a second current in said bit line of said second group;

wherein said reading said second non-volatile storage element comprises reading said second non-volatile storage element while said first current and said second current are in said bit line of said second group of non-volatile storage elements if said third non-volatile storage element is programmed to said first programmed state.

26. A method of reading non-volatile storage, comprising:

determining which non-volatile storage elements of a set of non-volatile storage elements are programmed to a first programmed state, said non-volatile storage elements of said set are coupled to a first word line and consecutive bit lines;

providing an initialization voltage to a bit line of each non-volatile storage element that is programmed to said first programmed state, said providing resulting in a first current in a bit line of each non-volatile storage element that was determined not to be programmed to said first programmed state; and

reading each non-volatile storage element that was determined not to be programmed to said first programmed state while said first currents are in said bit lines of said non-volatile storage elements that were determined not to be programmed to said first programmed state.

27. The method of claim 26, wherein:

said set of non-volatile storage elements includes a single page of data.

28. The method of claim 27, wherein:

said set of non-volatile storage elements is programmed using full-sequence programming.

29. The method of claim 26, wherein:

said set of non-volatile storage elements includes a first page of data and a second page of data;

each non-volatile storage element of said set stores a portion of said first page of data and said second page of data; and

said set of non-volatile storage elements is programmed by programming said first page of data and said second page of data at different times.

30. A non-volatile memory system, comprising:

a first group of non-volatile storage elements coupled to a first bit line;

a second group of non-volatile storage elements coupled to a second bit line; and

at least one sense block in communication with said first group of non-volatile storage elements and said second group of non-volatile storage elements, said at least one sense block;

reads a first non-volatile storage element of said first group of non-volatile storage elements to determine whether said first non-volatile storage element is programmed to a first programmed state,

provides an initialization voltage to said first bit line if said first non-volatile storage element is determined to be in said first programmed state, said initialization voltage results in a first current in said second bit line, and

reads a second non-volatile storage element of said second group while said first current is in said second bit line if said first non-volatile storage element is programmed to said first programmed state.

31. The non-volatile memory system of claim 30, wherein:

said at least one sense block includes a first sense block in communication with said first group of non-volatile storage elements and a second sense block in communication with said second group of non-volatile storage elements;

said first sense block reads said first non-volatile storage element and provides said initialization voltage; and

said second sense block reads said second non-volatile storage element.

32. The non-volatile memory system of claim 30, wherein:

said sense block includes at least one of sense circuitry and a processor.

33. The non-volatile memory system of claim 30, further comprising:

at least one managing circuit in communication with said at least one sense block; and

wherein said at least one sense block is under the control of said at least one managing circuit.

34. The non-volatile memory system of claim 33, wherein:

said at least one managing circuit includes a state machine.

35. A method of reading data from non-volatile storage, comprising:

receiving a request to read a first non-volatile storage element;

reading a second non-volatile storage element adjacent to said first non-volatile storage element in response to said request;

providing an initialization voltage to a bit line of said second non-volatile storage element if said second non-volatile storage element is programmed to at least one predetermined state, said initialization voltage resulting in a first current in a bit line of said first non-volatile storage element; and

reading said first non-volatile storage element while said first current is in said bit line of said first non-volatile storage element.

36. The method of claim 35, wherein:

said request is a request associated with reading said first non-volatile storage element using a first reference read voltage;

said reading said second non-volatile storage element is performed using a second reference read voltage; and

said reading said first non-volatile storage element is performed using said first reference read voltage and is performed after said reading said second non-volatile storage element.

37. The method of claim 36, wherein:

said reading said first non-volatile storage element is a second reading of said first non-volatile storage element; and

said reading said second non-volatile storage element includes a first reading of said first non-volatile storage element using said second reference read voltage.

38. The method of claim 35, wherein:

said bit line of said first non-volatile storage element is an odd bit line; and

said bit line of said second non-volatile storage element is an even bit line.

39. The method of claim 35, wherein:

said bit line of said first non-volatile storage element is an even bit line; and

said bit line of said second non-volatile storage element is an odd bit line.

40. The method of claim 35, wherein:

said at least one predetermined state includes a plurality of states.

41. The method of claim 40, wherein:

said providing comprises providing a same initialization voltage regardless of which state of said plurality of states said second non-volatile storage element is in.

42. The method of claim 40, wherein:

said plurality of states includes at least a first state and a second state; and

said step of providing comprises applying a first initialization voltage if said second non-volatile storage element is in said first programmed state and a second initialization voltage if said second non-volatile storage element is in said second programmed state.

43. The method of claim 40, wherein:

said plurality of states includes at least a first state and a second state; and

said step of reading said first non-volatile storage element comprises sensing a conduction current of said first non-volatile storage element during a first sampling period if said second non-volatile storage element is programmed to said first state and sensing said conduction current of said first non-volatile storage element during a second sampling period if said second non-volatile storage element is programmed to said second state.

44. The method of claim 35, wherein:

said first non-volatile storage element and said second non-volatile storage element each store a portion of a single page of data.

45. The method of claim 35, wherein:

said first non-volatile storage element and said second non-volatile storage element each store a portion of a first page of data and a portion of a second page of data.

46. The method of claim 35, wherein:

said second non-volatile storage element and said first non-volatile storage element are each coupled to a first word line.

47. The method of claim 35, wherein:

said first non-volatile storage element is coupled to a first word line; and

said second non-volatile storage element is coupled to a second word line.

48. The method of claim 35, further comprising:

reading a third non-volatile storage element adjacent to said first non-volatile storage element in response to said request; and

providing said initialization voltage to said bit line of said third non-volatile storage element if said third non-volatile storage element is programmed to said at least one predetermined state, said initialization voltage resulting in a second current in said bit line of said first non-volatile storage element;

wherein reading said first non-volatile storage element comprises reading said first non-volatile storage element while said first and second current are in said bit line of said first non-volatile storage element.

49. A non-volatile memory system, comprising:

a first group of non-volatile storage elements coupled to a first bit line;

a second group of non-volatile storage elements coupled to a second bit line; and

at least one sense block in communication with said first group of non-volatile storage elements and said second group of non-volatile storage elements, said at least one sense block;

receives a request to read a first non-volatile storage element of said first group,

reads at least one second non-volatile storage element of said second group in response to said request,

provides an initialization voltage to said second bit line if said second non-volatile storage element is programmed to at least one predetermined state, said initialization voltage resulting in a first current in said first bit line, and

reads said first non-volatile storage element while said first current is in said first bit line.

50. The non-volatile memory system claim 49, wherein:

said at least one predetermined state includes a plurality of states.

51. The non-volatile memory system of claim 50, wherein:

said providing comprises providing a same initialization voltage regardless of which state of said plurality of states said second non-volatile storage element is in.

52. The non-volatile memory system of claim 50, wherein:

said plurality of states includes at least a first state and a second state; and

said step of providing comprises applying a first initialization voltage if said second non-volatile storage element is in said first programmed state and a second initialization voltage if said second non-volatile storage element is in said second programmed state.

53. The non-volatile memory system of claim 49, wherein:

said second non-volatile storage element and said first non-volatile storage element are each coupled to a first word line.

54. The non-volatile memory system of claim 49, wherein:

said at least one sense block includes a first sense block in communication with said first group of non-volatile storage elements and a second sense block in communication with said second group of non-volatile storage elements;

said first sense block reads said first non-volatile storage element and provides said initialization voltage; and

said second sense block reads said second non-volatile storage element.

55. The non-volatile memory system of claim 49, wherein:

said sense block includes at least one of sense circuitry and a processor.

56. The non-volatile memory system of claim 49, further comprising:

at least one managing circuit in communication with said at least one sense block;

wherein said at least one sense block is under the control of said at least one managing circuit.