Monitoring the threshold voltage of frequently read cells

• US 7,193,901 B2
• Filed: 04/13/2005
• Issued: 03/20/2007
• Est. Priority Date: 04/13/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Eilert, Sean, Ruby, Paul
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/104,824
• Publication Number:
  US 20060233020A1
• Time in Patent Office: 706 Days
• Field of Search: 365/185.33, 365/185.09
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.

Claims

1. A method comprising:

providing a cell which gives an indication of a potential adverse situation before the situation actually affects data storing cells in a memory array by providing the cell with a higher drain bias so it experiences a read disturb before other cells on the same row.

2. The method of claim 1 including providing a cell, on each row in a memory array, said cell giving an early indication of a potential adverse situation.

3. The method of claim 1 wherein providing a cell includes providing a cell that gives an early warning of a read disturb.

4. The method of claim 1 wherein providing a cell includes providing a flash memory cell on a row of flash memory cells.

5. The method of claim 1 including providing a higher drain bias to said cell from a sense amplifier coupled to said cell.

6. The method of claim 1 including automatically storing data in a cache memory for subsequent access when said cell indicates a potential adverse situation.

7. The method of claim 1 including providing said cell on a row of flash memory cells and accessing a cache instead of said row in response to said cell indicating a potential adverse situation.

8. The method of claim 1 including providing a cell which provides an early indication of an excessive threshold voltage increase in a memory cell.

9. The method of claim 8 including automatically accessing a cache memory in place of a row in a semiconductor memory when said cell indicates an adverse situation.

10. A semiconductor memory comprising:

an array of memory cells to store data;

a detector cell coupled to said memory cells to indicate when the memory cells may become subject to an adverse condition in the future; and

a cache memory and a controller, said controller to automatically access said cache in response to the detection by said detector cell of said adverse condition.

11. The memory of claim 10 wherein said memory is a flash memory.

12. The memory of claim 10 including a word line, said memory cells arranged on said word line, said detector cell coupled to said word line.

13. The memory of claim 10 wherein said detector cell receives a different bias than said memory cells.

14. The memory of claim 13 including sense amplifiers, each of said memory cells coupled to a different sense amplifier.

15. The memory of claim 14 wherein said detector cell receives a higher drain bias than said memory cells.

16. The memory of claim 10 wherein said detector cell provides an indication of when the memory cells may become subject to a read disturb.

17. The memory of claim 10 wherein said detector cell is on a word line of said memory, said word line including said memory cells, said cache to store the data previously stored on said word line in response to the detection of said adverse condition.

18. The memory of claim 17 wherein said cache line to store data in place of said memory cells after said adverse condition is detected.

19. The memory of claim 10 wherein said detector cell to detect an increased threshold voltage.

20. An article comprising a medium storing instructions that, if executed, enable a processor-based system to:

prevent a read disturb by caching data stored in a memory upon detecting the possibility of a read disturb; and

flag a word line to prevent the word line from being accessed and to access instead data stored in a cache.

21. The article of claim 20 further storing instructions that, if executed, enable the processor-based system to detect whether a memory cell, exposed to a drain bias higher than the drain bias of other cells in said memory, is programmed.

22. A system comprising:

a controller;

a semiconductor memory including a canary cell to detect a read disturb, a word line, a plurality of memory cells on said word line, and said canary cell on said word line; and

a static random access memory coupled to said controller.

23. The system of claim 22 wherein said semiconductor memory is a flash memory.

24. The system of claim 22 wherein said canary cell is biased differently than said memory cells so that it experiences a read disturb before said memory cells.

25. The system of claim 24 including a cache memory in said semiconductor memory, said cache memory to replace said word line when said canary cell detects a read disturb.