Voltage regulating circuit and method of regulating voltage

• US 7,193,906 B2
• Filed: 12/10/2004
• Issued: 03/20/2007
• Est. Priority Date: 02/06/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jang, Ji Eun, Park, Kee Teok
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/008,672
• Publication Number:
  US 20050174864A1
• Time in Patent Office: 830 Days
• Field of Search: 365/189.09, 365/226, 327640-541, 232/277, 232/280
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.

Claims

1. A voltage regulating circuit comprising:

a core voltage terminal to which a core voltage of a semiconductor memory device is supplied;

a reference voltage generator for outputting a reference voltage by dividing the core voltage;

a controller for changing the reference voltage in response to a test mode voltage-up signal and a test mode voltage-down signal in a test mode without adjusting the core voltage;

a bitline precharge voltage generator for outputting a bitline precharge voltage in response to the reference voltage; and

a cell plate voltage generator for outputting a cell plate voltage in response to the reference voltage, and

wherein the test mode voltage-up and voltage-down signals are independently controlled.

2. The voltage regulating circuit as set forth in claim 1, wherein the reference voltage generator makes the reference voltage in accordance with a ratio of resistors connected in series.

3. The voltage regulating circuit as set forth in claim 1, wherein the controller comprises:

an inverter inverting the test mode voltage-up signal;

a first transistor for increasing the reference voltage by inactivating one of the resistors of the reference voltage generator, being driven responding to an output signal of the inverter; and

a second transistor for decreasing the reference voltage by inactivating the other of the resistors of the reference voltage generator, being driven responding to the test mode voltage-down signal.

4. The voltage regulating circuit as set forth in claim 1, wherein the reference voltage generator comprises:

a first resistor, a second resistor, a third resistor and a fourth resistor which are connected in series between the core voltage terminal and a ground terminal, wherein the sum of the first and second resistors is same as that of the third and fourth resistors.

5. The voltage regulating circuit as set forth in claim 1, wherein the first transistor includes a PMOS transistor and the second transistor includes an NMOS transistor.

6. A voltage regulating circuit comprising:

a core voltage terminal to which a core voltage of a semiconductor memory device is supplied;

a reference voltage generator for outputting a reference voltage by dividing the core voltage in accordance with a ratio of resistors connected between the core voltage terminal and a ground terminal;

an inverter inverting a test mode voltage-up signal;

a first transistor for increasing the reference voltage by inactivating one of the resistors which is connected to the core voltage terminal in response to an inverted test mode voltage-up signal without adjusting the core voltage;

a second transistor for decreasing the reference voltage by inactivating the other one of the resistors which is connected to the ground terminal in response to a test mode voltage-down signal without adjusting the core voltage;

a bitline precharge voltage generator for outputting a bitline precharge voltage in response to the reference voltage; and

a cell plate voltage generator for outputting a cell plate voltage in response to the reference voltage, and

wherein the test mode voltage-up and voltage-down signals are independently controlled.

7. The voltage regulating circuit as set forth in claim 6, wherein the first transistor is connected between the core voltage terminal and a first node and the second transistor is connected between a second node and the ground terminal.

8. The voltage regulating circuit as set forth in claim 6, wherein the reference voltage generator comprises:

a first resistor, a second resistor, a third resistor and a fourth resistor which are connected in series between the core voltage terminal and a ground terminal, wherein the sum of the first and second resistors is same as that of the third and fourth resistors.

9. The voltage regulating circuit as set forth in claim 6, wherein the first transistor includes a PMOS transistor and the second transistor includes an NMOS transistor.

10. A method of regulating a voltage, comprising:

generating a bitline precharge voltage and/or a cell plate voltage with using a reference voltage provided from a reference voltage generator in response to a core voltage;

increasing the reference voltage by controlling the reference voltage generator in response to an inverted test mode voltage-up signal without adjusting the core voltage and increasing the bitline precharge voltage and/or the cell plate voltage with using the increased reference voltage; and

decreasing the reference voltage by controlling the reference voltage generator in response to test mode voltage-down signal without adjusting the core voltage and decreasing the bitline precharge voltage and/or the cell plate voltage with using the decreased reference voltage, and wherein the test mode voltage-up and voltage-down signals are independently controlled.