Cascade wake-up circuit preventing power noise in memory device

• US 7,193,921 B2
• Filed: 04/11/2005
• Issued: 03/20/2007
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Choi, Hyun-su, Kim, Kyeong-rae
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/103,047
• Publication Number:
  US 20050286322A1
• Time in Patent Office: 708 Days
• Field of Search: 365/229, 365/194, 365/226, 365/154
• US Class Current: 365/229
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

Claims

1. A wake-up circuit of a memory device in which bit line pairs connected to a plurality of memory cells are precharged through a delay chain structure, the wake-up circuit comprising:

a plurality of bit line pairs corresponding to a plurality of memory blocks;

a wake-up control signal outputting unit that outputs a control signal for precharging the bit line pairs in order to wake-up the memory device from a sleep mode to an active mode; and

a plurality of precharge delay units that transmits the control signal to bit line pairs associated with a subsequent memory block when the output control signal and bit line pairs within a previous memory block have undergone a wake-up operation.

2. The wake-up circuit of claim 1, wherein the control signal output from the wake-up control signal outputting unit is sequentially output to bit line pairs of the plurality of memory blocks via the precharge delay units.

3. The wake-up circuit of claim 1, further comprising:

connection units that transmit the control signalto the bit lines; and

precharge circuits respectively precharging the bit line pairs,

wherein each connection unit includes;

a NAND gate that performs a NAND operation on the control signal and a precharge signal; and

a connection delay unit that delays the output of the NAND gate and that outputs the delayed output to the bit line pair.

4. The wake-up circuit of claim 3, wherein the connection delay unit includes a plurality of inverters.

5. The wake-up circuit of claim 4, wherein the control signal output from the connection delay unit is input to a precharge switch unit to deliver a power supply voltage to the bit line pair.

6. The wake-up circuit of claim 1, wherein the precharge delay unit includes:

a first switch that delivers a signal from the bit line pairs to a first node in response to an output signal of the precharge delay unit;

a NAND gate that performs a NAND operation on the control signal received from the previous block and a signal received from the first node and that outputs the result to a second node;

a second switch that delivers a power supply voltage to the first node in response to a signal received from the second node; and

an inverter that inverts the signal received from the second node and that transmits the control signal as the output signal of the precharge delay unit to the subsequent block.

7. The wake-up circuit of claim 6, wherein the first and second switches are PMOS transistors.

8. The wake-up circuit of claim 1, wherein the memory device is an SRAM (static random access memory) device.

9. A memory device comprising:

a plurality of memory cells;

a plurality of bit line pairs connected to the plurality of memory cells and divided into a plurality of memory blocks;

a wake-up control signal outputting unit that outputs a control signal for precharging the bit line pairs in order to wake up the memory device from a sleep mode to an active mode; and

a plurality of precharge delay units that transmit the control signal to bit line pairs associated with a subsequent memory block when the output control signal and bit line pairs within a previous memory block are determined to have performed a wake-up operation.

10. The memory device of claim 9, further comprising:

connection units that transmit the control signal to the bit lines; and

precharge circuits respectively precharging the bit line pairs,

wherein each connection unit includes;

a NAND gate that performs a NAND operation on the control signal and a precharge signal; and

a connection delay unit that delays the output of the NAND gate and that outputs the delayed output to the bit line pair.

11. The memory device of claim 10, wherein the connection delay unit includes a plurality of inverters.

12. The memory device of claim 11, wherein the control signal output from the connection delay unit is input to a precharge switch unit to deliver a power supply voltage to the bit line pair.

13. The memory device of claim 9, wherein the precharge delay unit includes:

a first switch that delivers a signal from the bit line pairs to a first node in response to an output signal of the precharge delay unit;

a NAND gate that performs a NAND operation on the control signal received from the previous block and a signal received from the first node and that outputs the result to a second node;

a second switch that delivers a power supply voltage to the first node in response to a signal received from the second node; and

an inverter that inverts the signal received from the second node and that transmits the control signal as the output signal of the precharge delay unit to the subsequent block.

14. The memory device of claim 13, wherein the first and second switches are PMOS transistors.

15. The memory device of claim 9, wherein the memory device is an SRAM device.

16. A wake-up method of a memory device in which bit line pairs of a plurality of memory cells divided into a plurality of memory blocks connected to a single word line are transitioned from a sleep mode to an active mode, the wake-up method comprising:

outputting a wake-up control signal;

precharging the bit line pairs corresponding to one of the memory blocks;

determining whether the bit line pairs within the one of the blocks have undergone a wake-up operation; and

transmitting the wake-up control signal to bit line pairs corresponding to a subsequent block if the bit line pairs of the one of the blocks have undergone the wake-up operation.

17. The wake-up method of claim 16, wherein determining includes:

feeding back precharge voltages of the bit line pairs within the one of the blocks to a control signal delay unit in response to the wake-up control signal; and

performing a logic operation on the precharge voltages of the bit line pairs corresponding to the one of the blocks and the wake-up control signal and outputting the result of the logic operating in the control signal delay unit.

18. The wake-up method of claim 16, wherein the memory device is an SRAM device.