Cascade wake-up circuit preventing power noise in memory device
First Claim
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1. A wake-up circuit of a memory device in which bit line pairs connected to a plurality of memory cells are precharged through a delay chain structure, the wake-up circuit comprising:
- a plurality of bit line pairs corresponding to a plurality of memory blocks;
a wake-up control signal outputting unit that outputs a control signal for precharging the bit line pairs in order to wake-up the memory device from a sleep mode to an active mode; and
a plurality of precharge delay units that transmits the control signal to bit line pairs associated with a subsequent memory block when the output control signal and bit line pairs within a previous memory block have undergone a wake-up operation.
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Abstract
A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.
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Citations
18 Claims
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1. A wake-up circuit of a memory device in which bit line pairs connected to a plurality of memory cells are precharged through a delay chain structure, the wake-up circuit comprising:
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a plurality of bit line pairs corresponding to a plurality of memory blocks; a wake-up control signal outputting unit that outputs a control signal for precharging the bit line pairs in order to wake-up the memory device from a sleep mode to an active mode; and a plurality of precharge delay units that transmits the control signal to bit line pairs associated with a subsequent memory block when the output control signal and bit line pairs within a previous memory block have undergone a wake-up operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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a plurality of memory cells; a plurality of bit line pairs connected to the plurality of memory cells and divided into a plurality of memory blocks; a wake-up control signal outputting unit that outputs a control signal for precharging the bit line pairs in order to wake up the memory device from a sleep mode to an active mode; and a plurality of precharge delay units that transmit the control signal to bit line pairs associated with a subsequent memory block when the output control signal and bit line pairs within a previous memory block are determined to have performed a wake-up operation. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A wake-up method of a memory device in which bit line pairs of a plurality of memory cells divided into a plurality of memory blocks connected to a single word line are transitioned from a sleep mode to an active mode, the wake-up method comprising:
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outputting a wake-up control signal; precharging the bit line pairs corresponding to one of the memory blocks; determining whether the bit line pairs within the one of the blocks have undergone a wake-up operation; and transmitting the wake-up control signal to bit line pairs corresponding to a subsequent block if the bit line pairs of the one of the blocks have undergone the wake-up operation. - View Dependent Claims (17, 18)
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Specification