Multi-pair gigabit ethernet transceiver having adaptive disabling or circuit elements

• US 7,194,029 B2
• Filed: 10/08/2003
• Issued: 03/20/2007
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kruse, David E., Hatamian, Mehdi, Creigh, John L., Agazzi, Oscar E., Samueli, Henry, Abnous, Arthur
• Primary Examiner(s): Corrielus; Jean B.
• Application Number:
  US10/681,444
• Publication Number:
  US 20040091038A1
• Time in Patent Office: 1,259 Days
• Field of Search: 375/233, 375/285, 375/229, 375/254, 375259-260, 375/346, 375/348, 375/350, 375/262, 375/265, 375/224, 375/227, 375/286
• US Class Current: 375/233
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 : not time-recursive
• CPC Class Codes: H04L 2025/0349 : as a feedback filter
• CPC Class Codes: H04L 2025/03496 : as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03235 : with state-reduction using feedback filtering
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03987 : Equalisation for sparse channels
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Claims

1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:

a trellis decoder adapted to decode an input sample into a final decision corresponding to a codeword of a trellis code;

an intersymbol interference (ISI) compensation circuit configured to compensate for an ISI component;

adaptive circuitry operable to reduce power consumption of a filter having a plurality of taps, the adaptive circuitry operable to one of activate and deactivate selected taps of the filter based on an error metric and a power metric.

2. The integrated circuit communication device according to claim 1, wherein each tap of the filter has an associated coefficient, wherein the adaptive circuitry is operable to compare the coefficient associated with a given tap to a threshold value and wherein the adaptive circuitry is operable to one of activate and deactivate the given tap based on said comparison.

3. The integrated circuit communication device according to claim 2, wherein the adaptive circuitry is operable to deactivate the given tap if the coefficient has a value smaller than the threshold.

4. The integrated circuit communication device according to claim 3, further comprising:

an error computing module computing the error metric; and

wherein the adaptive circuitry is operable to compare the error metric with a specified error.

5. The integrated circuit communication device according to claim 4, wherein the adaptive circuitry is operable to update the threshold based on the comparison of the error metric with the specified error.

6. The integrated circuit communication device according to claim 1, wherein the ISI compensation circuit comprises:

an inverse partial response filter having an impulse response substantially an inverse of an impulse response of a pulse shaping filter of a remote transmitter, so as to substantially compensate an input digital signal for an ISI component.

7. The integrated circuit communication device according to claim 6, wherein the inverse partial response filter is implemented with a characteristic feedback gain factor K.

8. The integrated circuit communication device according to claim 7, wherein the inverse partial response filter operates in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and wherein the value of the feedback gain factor K is ramped down to zero after a pre-defined interval.

9. The integrated circuit further communication device according to claim 8, wherein the ISI compensation circuit comprises:

feedback equalizer circuitry coupled to the trellis decoder, the feedback equalizer circuitry receiving tentative decisions from the trellis decoder and combining the tentative decisions with a set of high-ordered coefficients to generate a first value.

10. The integrated circuit communication device according to claim 9, wherein the intersymbol interference (ISI) compensation circuit further comprises:

summing circuitry combining the first value with a digital signal, the summing circuitry outputting an intermediate signal; and

a multiple decision feedback equalizer receiving the intermediate signal and combining the intermediate signal with a set of pre-computed values generated by combining values of a set of low-ordered coefficients with a set of values representing levels of a multi-level symbolic alphabet to produce a set of potential digital signals, one of the potential digital signals being substantially ISI compensated, the multiple decision feedback equalizer outputting said one of the potential digital signals to the trellis decoder.

11. The integrated circuit communication device according to claim 10, wherein the characteristic feedback gain factor K is ramped to zero after convergence of the feedback equalizer circuitry.

12. The integrated circuit communication device according to claim 9, the feedback equalizer circuitry having a set of ordered coefficients, the feedback equalizer circuitry defining a coefficient related tail value and a low order subset of coefficient values.

13. The integrated circuit communication device according to claim 12, wherein the feedback equalizer circuitry has a width dimension D, wherein the width dimension D corresponds to the number of pairs defining the multi-pair transmission channel.

14. The integrated circuit communication device according to claim 13, further comprising a state multiplication circuit, the state multiplication circuit expanding a single state representation output signal received from the feedback equalizer circuitry into an N-state representation signal suitable for decoding by the trellis decoder.

15. The integrated circuit communication device according to claim 14, the state multiplication circuit comprising:

a convolution engine coupled to combine the low order subset of coefficient values with each member of a set of symbolic levels to define a first sample signal set; and

a summing circuit coupled to combine the tail value with each member of the first sample signal set to define an N state representational set of signal samples.