Digital automatic level control system

• US 7,194,049 B2
• Filed: 10/15/2002
• Issued: 03/20/2007
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Dhalla, Cyrus A., Munoz, Michael S.
• Primary Examiner(s): Patel; Jay K.
• Assistant Examiner(s): Wang; Ted M.
• Application Number:
  US10/271,100
• Publication Number:
  US 20040071236A1
• Time in Patent Office: 1,617 Days
• Field of Search: 375/345, 375/316, 455/136, 455/138, 455/239.1, 455/240.1, 455/242.1, 455/245.1, 455/250.1
• US Class Current: 375/345
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

A digital automatic level control system employs delay elements, which enable information about a signal parameter from the past, present and future to be processed to provide an optimal gain that can be used to level rapidly varying signals, such as bursty signals. As digital time samples of a signal are passed through first and second buffers, first and second accumulators maintain running sums that are related to the sum of the samples presently in the first and second buffers, respectively. The sums in the first and second accumulators represent information about the signal parameter for the future and the past, respectively. By choosing the maximum of these two values, the system can anticipate the beginning of a signal burst, and still have enough delay to compensate the end of a signal burst. In one embodiment of the invention, multiple channel signals can be leveled, either individually or in groups.

Claims

1. A digital automatic level control (DALC) system comprising:

a level detector module including;

a first digital delay element having an input for receiving a sequence of inputted digital time samples of a signal to be leveled and an output for sequentially outputting a first sequence of outputted time samples after a pre-selected delay;

a first accumulator for receiving said sequence of inputted time samples and adding each of said inputted samples to a first running sum, and for receiving said sequence of outputted time samples on said output of said delay element and subtracting each of said outputted time samples from said first running sum, whereby said first running sum is representative of the average value of all time samples presently contained in said first delay element;

a second digital delay element having an input for receiving said sequence of outputted digital time samples from said output of said first digital delay element and an output for sequentially outputting a second sequence of outputted time samples after a predetermined delay; and

a second accumulator for receiving said first sequence of outputted time samples and adding each of said first sequence of outputted time samples to a second running sum, and for receiving said second sequence of outputted time samples on said output of said second delay element and subtracting each of said outputted time samples in said second sequence from said second running sum, whereby said second running sum is representative of the average value of all time samples presently contained in said second delay element; and

a level adjustment module for employing the greater of said first and second running sums to form a level adjusted output sequence of digital time samples.

2. The DALC system of claim 1, wherein said first and second digital delay elements comprise first and second digital buffers.

3. The DALC system of claim 1, further comprising first, second and third processing elements, said first processing element being disposed between said input of said first delay element and said input of said first accumulator for processing said inputted sequence of time samples prior to adding said inputted sequence of time samples to said first running sum in said first accumulator;

a second processing element disposed between said output of said first delay element and said inputs of said first and second accumulators for processing said first outputted sequence of time samples prior to said first outputted sequence of time samples being subtracted from said first running sum in said first accumulator and added to said second running sum in said second accumulator; and

, a third processing element disposed between said output of said second digital delay element and said input of said second accumulator for processing said time samples in said second outputted sequence prior to being subtracted from said second running sum in said second accumulator.

4. The DALC system of claim 3, wherein said processing elements comprise first, second and third squarers for squaring said inputted time samples, said time samples in said first outputted sequence and said time samples in said second outputted sequence, respectively, whereby, said first running sum is proportional to the average power of said time samples contained in said first delay element and said second running sum is proportional to the average power of said time samples contained in said second delay element.

5. The DALC system of claim 4, wherein said level adjustment module includes:

a square root calculating element for calculating and outputting a square root of the greater of said first and second running sums in said first and second accumulators, respectively;

a first multiplier for multiplying said output from said square root calculating element by a constant and thereby generating a gain coefficient; and

a second multiplier for multiplying said outputted samples in said first sequence by said gain coefficient, thereby forming a level adjusted output sequence of digital time samples.

6. The DALC system of claim 3, wherein said processing elements comprise first, second and third absolute value calculating elements for generating an absolute value of said inputted time samples, said time samples in said first outputted sequence and said time samples in said second outputted sequence, respectively.

7. The DALC system of claim 1, wherein said level adjustment module includes:

a first multiplier for multiplying the greater of said first and second running sums in said first and second accumulators, respectively, by a constant and thereby generating a gain coefficient; and

a second multiplier for multiplying said outputted samples in said first sequence by said gain coefficient, thereby forming a level adjusted output sequence of digital time samples.

8. The DALC system of claim 7, wherein said level adjustment module further includes a max selector element for comparing said first and second running sums and supplying the greater of said sums to said first multiplier.

9. The DALC system of claim 7, wherein said level adjustment module further includes a thresholder for receiving the greater of said sums from said max selector element and directing the greater of said sums to said first multiplier only if the greater of said sums exceeds a predetermined threshold value.

10. The DALC system of claim 7, wherein said level adjustment module further includes a mode selector for selecting among an automatic level control mode, a fixed gain mode in which a fixed gain coefficient is supplied to said second multiplier and a no gain mode in which a gain coefficient of unity is supplied to said second multiplier.

11. The DALC system of claim 1, wherein said inputted sequence of time samples includes samples from a plurality of signals and a group selector is provided for instructing said first and second accumulators to group samples from each of said signals together into a plurality running sums, one in each said accumulator for each of said signals.

12. The DALC system of claim 1, wherein said level detector and said level adjustment modules are formed on a single application specific integrated circuit.

13. A method for automatically controlling the level of one or more digital signals comprising the steps of:

providing an input sequence of digital time samples of at least one signal to be leveled;

adding each of said time samples in said sequence to a first running sum;

passing said input sequence of digital time samples through a first digital delay element, thereby forming a first outputted sequence of digital time samples;

subtracting each of said time samples in said first outputted sequence from said first running sum as they are outputted from said first digital delay element, whereby said first running sum is representative of the average value of all time samples presently contained in said first delay element;

adding each of said time samples in said first outputted sequence to a second running sum as they are outputted from said first digital delay element;

passing said first outputted sequence of digital time samples through a second first digital delay element, thereby forming a second outputted sequence of digital time samples;

subtracting each of said time samples in said second outputted sequence from said second running sum as they are outputted from said second digital delay element, whereby said second running sum is representative of the average value of all time samples presently contained in said second delay element; and

employing the greater of said first and second running sums to form a level adjusted output sequence of digital time samples.

14. The method of claim 13, wherein said first and second digital delay elements are selected to be first and second digital buffers.

15. The method of claim 13, further comprising the steps of processing said inputted sequence of time samples prior to adding said inputted sequence of time samples to said first running sum, processing said first outputted sequence of time samples prior to said first outputted sequence of time samples being subtracted from said first running sum and added to said second running sum, and processing said time samples in said second outputted sequence prior to being subtracted from said second running sum.

16. The method of claim 15, wherein said steps of processing further comprise squaring said inputted time samples, said time samples in said first outputted sequence and said time samples in said second outputted sequence, whereby, said first running sum is proportional to the average power of said time samples contained in said first delay element and said second running sum is proportional to the average power of said time samples contained in said second delay element.

17. The method of claim 16, wherein said step of employing the greater of said first and second running sums to adjust the level of each of said outputted samples in said first outputted sequence further comprises:

calculating a square root of the greater of said first and second running sums;

multiplying said square root by a constant and thereby generating a gain coefficient; and

multiplying said samples in said first outputted sequence by said gain coefficient, thereby forming a level adjusted output sequence of digital time samples.

18. The method of claim 15, wherein said steps of processing further comprise calculating the absolute values of said inputted time samples, said time samples in said first outputted sequence and said time samples in said second outputted sequence.

19. The method of claim 13, wherein said step of employing the greater of said first and second running sums to adjust the level of each of said outputted samples in said first outputted sequence further comprises:

multiplying the greater of said first and second running sums by a constant and thereby generating a gain coefficient; and

multiplying said samples in said first outputted sequence by said gain coefficient, thereby forming a level adjusted output sequence of digital time samples.

20. The method of claim 13, wherein said inputted sequence of time samples includes samples from a plurality of signals and said method further comprises the steps of grouping samples from each of said signals together and forming a plurality of running sums during said adding and subtracting steps, one for each signal having samples in said first delay element and one for each signal having samples in said second delay element.