Method and apparatus for scheduling requests to a resource using a configurable threshold

• US 7,194,561 B2
• Filed: 10/12/2001
• Issued: 03/20/2007
• Est. Priority Date: 10/12/2001
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Weber, Wolf-Dietrich
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/977,600
• Publication Number:
  US 20030074504A1
• Time in Patent Office: 1,985 Days
• Field of Search: 710/112, 710/116, 710/117, 710/118, 710/308, 710/309, 710/310, 710/311, 710/316, 711/105, 711/147, 711/154, 711/167
• US Class Current: 710/31
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.

Claims

1. A method for scheduling access to a device comprising:

tracking a current state of a device;

tracking a count of a number of scheduled requests which require the current state;

storing a configurable switch point, wherein the configurable switch point includes a threshold value to indicate when to switch from the current state to an alternate state of the device; and

switching the state of the device after;

determining the count reaches the threshold value established for the switch point; and

receiving one or more incoming requests which require the alternate state of the device.

2. The method as set forth in claim 1, further comprising configuring the switch point.

3. The method as set forth in claim 2, wherein the switch point is dynamically configurable by software.

4. The method as set forth in claim 1, wherein the device is a dynamic random access memory (DRAM), the method further comprising selecting a scheduler type from the group consisting of a DRAM bus turnaround scheduler, a DRAM page scheduler, and a DRAM physical bank switching scheduler.

5. A bus scheduler comprising:

an input configured to receive at least one incoming request, each request indicating a bus direction;

a register to store a configurable switch point, wherein the configurable switch point includes a threshold value to indicate when to switch from the current state to an alternate state of the device;

an indicator of a current bus direction;

a unit to track a count of requests processed using the current bus direction; and

logic configured to switch the direction of the bus to process incoming requests after the count reaches the threshold value established for the switch point and there are incoming requests having the direction opposite to the current direction of the device bus.

6. The bus scheduler as set forth in claim 5, wherein the threshold value established for the switch point is dynamically configurable.

7. The bus scheduler as set forth in claim 5, wherein the bus scheduler is embedded on a System on a Chip.

8. The bus scheduler as set forth in claim 5, further comprising:

a controller of a volatile memory coupled to the scheduler via the bus; and

filter logic configured to combine thread quality of service scheduling and volatile memory scheduling to reorder servicing requests from one or more threads based on achieving a highest usage efficiency of the volatile memory while still satisfying quality of service guarantees for each thread.

9. The apparatus of claim 8, wherein the logic is further configured to empirically determine the switch point based upon past performance of the filter logic.

10. The apparatus of claim 9, wherein the logic is further configured to implement a count and compare function to determine the switch point.

11. The apparatus of claim 5, further comprising reset logic to reset the count.

12. The apparatus of claim 11, wherein the unit is further configured to restart the count in response to a count reset and a determination that there are the incoming requests having a direction opposite to the current direction of the device bus.

13. A scheduler comprising:

a first unit to track a current state of a device;

a second unit to track a count of requests that require a particular state;

a register to store a configurable switch point, wherein the configurable switch point includes a threshold value to indicate when to switch from the current state to an updated device state;

logic configured to facilitate the updated device state when the count crosses the threshold of the switch point; and

scheduling logic configured to schedule access requests to the device using the updated device state.

14. The scheduler as set forth in claim 13, wherein a value of the threshold established for the switch point is dynamically configurable via software.

15. The scheduler as set forth in claim 13 wherein the device comprises a bus and the device state comprises a bus direction, said scheduling dependent upon the bus direction.

16. The scheduler as set forth in claim 13, wherein the device is a dynamic random access memory (DRAM) and scheduling is selected from the group consisting of DRAM bus turnaround scheduling, DRAM page scheduling and DRAM physical bank switching.

17. The scheduler as set forth in claim 13, wherein the device comprises a DRAM with multiple pages and the device state comprises the identity of at least one open page, said scheduling dependent on the at least one page opened.

18. The scheduler as set forth in claim 13, wherein the device comprises a DRAM with multiple physical banks and the device state comprises the last accessed physical bank, said scheduling dependent on the last accessed physical bank.

19. The scheduler as set forth in claim 13, wherein the scheduler is embedded on a System on a Chip.

20. The scheduler as set forth in claim 13, further comprising:

a controller of a volatile memory coupled to the scheduler; and

filter logic configured to combine thread quality of service scheduling and volatile memory scheduling to reorder servicing requests from one or more threads based on achieving a highest usage efficiency of the volatile memory while still satisfying quality of service guarantees for each thread.

21. The apparatus of claim 20, wherein the logic is further configured to empirically determine the switch point based upon past performance of the filter logic.

22. The apparatus of claim 21, wherein the logic is further configured to implement a count and compare function to determine the switch point.

23. The apparatus of claim 13, further comprising reset logic to reset the count.

24. The apparatus of claim 23, wherein the second unit is further configured to restart the count in response to a count reset and one or more incoming requests which require the updated device state.

25. An apparatus to scheduling access to a device comprising:

means for tracking a current state of a device;

means for tracking a count of a number of scheduled requests which require the current state;

means for storing a configurable switch point, wherein the configurable switch point includes a threshold value to indicate when to switch from the current state to an alternate state of the device; and

means for switching the state of the device after;

determining the count reaches the threshold value established for the switch point; and

receiving one or more incoming requests which require the alternate state of the device.