Memory hub with integrated non-volatile memory

• US 7,194,593 B2
• Filed: 09/18/2003
• Issued: 03/20/2007
• Est. Priority Date: 09/18/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Schnepper, Randy L.
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US10/665,904
• Publication Number:
  US 20050066136A1
• Time in Patent Office: 1,279 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory controller includes registers into which the memory configuration information is loaded and is operable to output memory requests in response to receiving memory access requests from the high-speed interface and in accordance with the memory configuration information loaded in the registers. A method for initializing a memory sub-system is also provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub.

Claims

1. A memory hub for a hub-based memory sub-system, comprising:

a link interface for receiving memory access requests;

an electrically programmable non-volatile memory having memory module configuration information stored therein;

a first configuration path coupled to the link interface and the electrically programmable non-volatile memory, the first configuration path configured to provide the link interface access to the electrically programmable non-volatile memory;

a second configuration path coupled to the electrically programmable non-volatile memory and configured to provide access to the electrically programmable non-volatile memory;

a local serial bus coupled to the electrically programmable non-volatile memory and configured to provide a host system access to the electrically programmable non-volatile memory; and

a memory controller coupled to the link interface and further coupled to the electrically programmable non-volatile memory through the second configuration path, the memory controller having registers into which the memory configuration information is loaded, the memory controller operable to access the electrically programmable non-volatile memory through the second configuration path and further operable to output memory requests in response to receiving memory access requests from the link interface and in accordance with the memory configuration information loaded in the registers.

2. The memory hub of claim 1 wherein the electrically programmable non-volatile memory comprises an embedded array of electrically erasable programmable read-only memory.

3. The memory sub-system of claim 1 wherein the memory configuration information comprises at least one of timing information for the plurality of memory devices of the memory module, memory module configuration data, memory device type, and manufacturer data.

4. The memory hub of claim 1 wherein the non-volatile memory is further coupled to the link interface.

5. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

an input/output channel coupled to the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the plurality of memory devices, comprising;

a link interface for receiving memory access requests from the system controller;

an electrically programmable non-volatile memory having memory module configuration information for the plurality of memory devices stored therein;

a first configuration path coupled to the link interface and the electrically programmable non-volatile memory, the first configuration path configured to provide the link interface access to the electrically programmable non-volatile memory;

a second configuration path coupled to the electrically programmable non-volatile memory and configured to provide access to the electrically programmable non-volatile memory;

a local serial bus coupled to the electrically programmable non-volatile memory and configured to provide a host system access to the electrically programmable non-volatile memory; and

a memory controller coupled to the link interface and further coupled to the electrically programmable non-volatile memory through the second configuration path, the memory controller operable to access the electrically programmable non-volatile memory through the second configuration path and further operable to output memory requests to the plurality of memory devices in response to receiving memory access requests from the link interface and in accordance with the memory configuration information stored by the electrically programmable non-volatile memory.

6. The processor-based system of claim 5 wherein the electrically programmable non-volatile memory comprises an embedded array of electrically erasable programmable read-only memory.

7. The processor-based system of claim 5 wherein the memory configuration information comprises at least one of timing information for the plurality of memory devices of the memory module, memory module configuration data, memory device type, and manufacturer data.

8. The processor-based system of claim 5 wherein the plurality of memory devices comprises synchronous dynamic random access memory devices.