Schottky diode device with aluminum pickup of backside cathode

• US 7,195,952 B2
• Filed: 03/22/2005
• Issued: 03/27/2007
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Alter, Martin, Vinn, Chuck
• Primary Examiner(s): Kebede; Brook
• Assistant Examiner(s): Kim; Su C.
• Application Number:
  US11/087,913
• Publication Number:
  US 20060216855A1
• Time in Patent Office: 735 Days
• Field of Search: 438106-108, 438/112, 438/25, 438/26, 257666-678, 257/686, 257/690, 257/703
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/2908 being stacked
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 29/417 : carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor

Abstract

An integrated circuit package includes a semiconductor chip having a passivation layer forming the top surface of the semiconductor chip and a metal pad formed on the passivation layer and a discrete electronic device having a first terminal formed on a first surface and a second terminal formed on a second surface opposite the first surface of the discrete electronic device where the first surface of the discrete electronic device is attached to the metal pad using a conductive adhesive structure. The semiconductor chip and the discrete electronic device are encapsulated in an encapsulation material. An electrical connection is formed between the metal pad and one of a bond pad of the semiconductor chip or a package post of the integrated circuit package. In one embodiment, the metal pad is an aluminum pad and a metal line connects the metal pad to a bond pad of the semiconductor chip.

Claims

1. A method for forming an integrated circuit package including a semiconductor chip having a passivation layer and a discrete electronic device, the method comprising:

providing a discrete electronic device having a first surface and a second surface opposite the first surface, the first surface comprising a single terminal being a backside electrode of the discrete electronic device, and the second surface comprises a second terminal, at least one of the backside electrode and the second terminal of the discrete electronic device being electronically coupled to the semiconductor chip;

forming a metal pad on the top surface of the passivation layer of the semiconductor chip;

attaching substantially the entire first surface of the discrete electronic device to the metal pad using a conductive adhesive structure to form an electrical connection between the backside electrode of the discrete electronic device and the metal pad;

forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package; and

encapsulating the semiconductor chip and the discrete electronic device to form the integrated circuit package.

2. The method of claim 1, wherein forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package comprises forming an electrical connection from the metal pad to a first bond pad of the semiconductor chip.

3. The method of claim 2, wherein forming an electrical connection from the metal pad to a first bond pad of the semiconductor chip comprises:

forming a metal line on the top surface of the passivation layer of the semiconductor chip, the metal line connecting the metal pad to the first bond pad.

4. The method of claim 3, wherein the first bond pad connects to circuitry of the semiconductor chip.

5. The method of claim 1, wherein forming an electrical connection from the metal pad to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package comprises forming an electrical connection from the metal pad to a first package post of the integrated circuit package.

6. The method of claim 5, wherein forming an electrical connection from the metal pad to a first package post of the integrated circuit package comprises:

connecting the metal pad to the first package post using a bond wire.

7. The method of claim 1, further comprising:

forming a second electrical connection using a bond wire from the second terminal on the second surface of the discrete electronic device to one of a bond pad of the semiconductor chip or a package post of the integrated circuit package.

8. The method of claim 1, wherein the metal pad comprises an aluminum pad.

9. The method of claim 1, wherein the conductive adhesive structure comprises a conductive epoxy.

10. The method of claim 9, wherein the conductive adhesive structure comprises a gold layer formed on the first surface of the discrete electronic device and a conductive epoxy layer formed on the gold layer for attaching to the metal pad.

11. The method of claim 10, wherein the gold layer is doped with 0.1% arsenic.

12. The method of claim 1 wherein the discrete electronic device comprises one of a Schottky diode, a VDMOS device, an NPN transistor and a PNP transistor.

13. The method of claim 1, further comprising:

prior to attaching the first surface of the discrete electronic device to the metal pad, roughening the first surface of the discrete electronic device using a coarse wheel grinder.