Method of manufacturing an intralevel decoupling capacitor

• US 7,195,971 B2
• Filed: 02/28/2005
• Issued: 03/27/2007
• Est. Priority Date: 06/11/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ning, Tak H., Cote, William J., Bernstein, Kerry, Bracchitta, John A., Pricer, Wilbur D.
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US11/066,738
• Publication Number:
  US 20050139959A1
• Time in Patent Office: 757 Days
• Field of Search: 438239-240, 438/253, 438/393, 438/396, 257/306, 257/307, 257/310
• US Class Current: 438/239
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Claims

1. A method of manufacturing a capacitor, the method comprising:

forming interdigitized metal wires on a first low dielectric material;

depositing a high dielectric material between said interdigitized metal wires; and

depositing a second low dielectric material on said high dielectric material such that said interdigitized metal wires are provided between said first and second low dielectric material.

2. The method of claim 1 further comprising:

depositing polish stop material at least on said metal wires prior to depositing said high dielectric material.

3. The method of claim 2 wherein said polish stop material comprises diamond-like carbon.

4. The method of claim 2 wherein said polish stop material comprises silicon nitride.

5. The method of claim 2 wherein said depositing said polish stop material comprises non-conformally depositing said polish stop material on said interdigitized metal wires.

6. The method of claim 1 wherein said polish stop material is also deposited on said first low dielectric material between said interdigitized metal wires.

7. The method of claim 6 further comprising:

etching back said high dielectric material at least to a top surface of said interdigitized metal wires.

8. The method of claim 7 wherein said etching back said high dielectric material comprises performing chemical mechanical polishing (CMP) of said high dielectric material down to said polish stop material.

9. The method of claim 1 wherein said high dielectric material comprises a dielectric constant that is higher than dielectric constants of said first and second low dielectric materials.

10. The method of claim 1 wherein said forming said interdigitized metal wires comprises:

patterning a first metal wire on said first low dielectric material; and

patterning a second metal wire on said first low dielectric material such that said second meal wire is interleaved with said first metal wire in a direction parallel to a plane of said first low dielectric material.

11. The method of claim 10 wherein said first and second metal wires comprise comb shaped patterns.

12. The method of claim 1 wherein said depositing said high dielectric material is performed after said forming said interdigitized metal wires.

13. The method of claim 1, wherein said high dielectric material comprises tantalum pentoxide.

14. The method of claim 1 wherein said first low dielectric material comprises silicon nitride.

15. The method of claim 1 wherein said first low dielectric material comprises fluorinated glass.

16. The method of claim 1 wherein an upper surface of said high dielectric material is coplanar with an upper surface of said interdigitized metal wires.

17. The method of claim 1 wherein sidewalls of adjacent fingers of said interdigitized metal wires form plates of said capacitor.

18. A method of manufacturing a capacitor, the method comprising:

patterning a first metal wire on a first layer of low dielectric material; and

patterning a second metal wire on said low dielectric material such that said second meal wire is interleaved with said first metal wire in a direction parallel to a plane of said first low dielectric material;

depositing a high dielectric material between said first and second metal wires; and

depositing a second layer of low dielectric material on said high dielectric material.