Termination design with multiple spiral trench rings

• US 7,196,397 B2
• Filed: 03/04/2005
• Issued: 03/27/2007
• Est. Priority Date: 03/04/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M., Andoh, Kohji, Zhi, He, Chiola, Davide
• Primary Examiner(s): Andujar; Leonardo
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US11/073,123
• Publication Number:
  US 20050230777A1
• Time in Patent Office: 753 Days
• Field of Search: 257/484, 257/483, 257/480, 257/531, 257/528, 257/E27.009, 257/E27.01, 257/E21.022, 438/379, 438/570
• US Class Current: 257/531
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Claims

1. A semiconductor device comprising:

an active region formed in a semiconductor body;

a termination region including a spiral trench formed in said semiconductor body disposed around said active region; and

an electrically conductive but resistive body disposed within said trench, said body including a first end and a second end, said first end being electrically connected to said active region, and said second end being electrically connected to a region of an electric potential in said termination region different from an electric potential of said active region, wherein said trench includes opposing walls and a bottom, and an insulation body disposed between said resistive body, said walls and said bottom of said trench.

2. A semiconductor device according to claim 1, wherein said insulation body is comprised of Si₂O.

3. A semiconductor device according to claim 1, wherein said resistive body is comprised of conductive poly silicon.

4. A semiconductor device according to claim 1, wherein said active region comprises an active region of a power diode, an IGBT or a power MOSFET.

5. A semiconductor device comprising:

an active region; and

a termination region, said termination region including;

a first spiral trench disposed around said active region;

a first resistive body disposed within said first trench;

a second spiral trench disposed around said active region, and spaced from said first spiral trench; and

a second resistive body disposed within said second spiral trench;

wherein each resistive body includes a first end electrically connected to said active region and a second end electrically connected to a region in said termination region.

6. A semiconductor device according to claim 5, wherein each trench includes opposing walls and a bottom, and further comprising an insulation body disposed between each resistive body, said walls and said bottom of a respective one of said trenches.

7. A semiconductor device according to claim 6, wherein said insulation body is comprised of Si₂O.

8. A semiconductor device according to claim 5, wherein said resistive body is comprised of conductive polysilicon.

9. A semiconductor device according to claim 5, wherein said active region comprises an active region of a power diode, an IGBT or a power MOSFET.

10. A semiconductor device according to claim 5, wherein said trenches are interleaved.

11. A semiconductor device according to claim 5, wherein said trenches are equidistant.

12. A semiconductor device according to claim 5, wherein said first end of said first resistive body is electrically connected to a first portion of said active region and said second end of said first resistive body to a first portion of said termination region, and said first end of said second resistive body is electrically connected to a second portion of said active region and said second end of said second resistive body is electrically connected to a second portion of said termination region.

13. A semiconductor device according to claim 5, wherein said termination region further includes a third spiral trench disposed around said active region;

a third resistive body disposed within said third spiral trench;

a fourth spiral trench disposed around said active region; and

a fourth resistive body disposed within said fourth spiral trench.

14. A semiconductor device according to claim 13, wherein each resistive body includes a first end electrically connected to a respective portion of said active region and a second end electrically connected to a respective region of said termination.

15. A semiconductor device according to claim 13, wherein said spiral trenches are interleaved.

16. A semiconductor device according to claim 13, wherein each trench is spaced from an adjacent trench by a respective distance, said distances being equal.