Programmable logic integrated circuit devices with low voltage differential signaling capabilities

• US 7,196,556 B1
• Filed: 01/22/2003
• Issued: 03/27/2007
• Est. Priority Date: 07/02/1998
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sung, Chiakang, Huang, Joseph, Wang, Xiaobao, Nguyen, Khai, Kim, In Whan, Yeung, Wayne, Wang, Bonnie I, Cliff, Richard G
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US10/350,551
• Time in Patent Office: 1,525 Days
• Field of Search: 327/108, 327/110, 327/112, 326/30, 326/83, 326/86
• US Class Current: 327/108
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Claims

1. Buffer circuitry configured to produce from an input signal indicative of information a pair of output signals that indicate the information by the relative polarity of their voltages comprising:

a source of relatively high voltage;

a source of relatively low voltage;

differential switching circuitry configured to produce the output signals in response to the input signal;

first resistor circuitry connected in series between the source of relatively high voltage and the differential switching circuitry; and

second resistor circuitry connected in series between the differential switching circuitry and the source of relatively low voltage, wherein;

connections between the sources, the differential switching circuitry, and the first and second resistor circuitries are such that when external circuitry is connected in series between the two output signals, current flows in series from the source of relatively high voltage through the first resistor circuitry, through the external circuitry, through the second resistor circuitry, to the source of relatively low voltage; and

at least one of the first and second resistor circuitries includes a transistor coupled in series with a first resistor and a second resistor and is configured to increase in resistance in response to an increase in voltage difference between the source of relatively high voltage and the source of relatively low voltage.

2. The buffer circuitry defined in claim 1 wherein transistors in the differential switching circuitry and the first and second resistor circuitries are configured to have similar changes in resistance due to variations in a manufacturing process for making an integrated circuit including those circuitries.

3. The buffer circuitry defined in claim 1 wherein transistors in the differential switching circuitry and the first and second resistor circuitries are configured to have similar changes in resistance due to changes in temperature of an integrated circuit including those circuitries.

4. The buffer circuitry defined in claim 1 further comprising:

circuitry configured to turn off the differential switching circuitry when it is not desired to use the output signals.

5. A programmable logic device having programmable logic circuitry comprising:

the buffer circuitry defined in claim 1, wherein the input signal is provided to the buffer circuitry by the logic circuitry of the device.

6. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a logic device as defined in claim 5 coupled to the processing circuitry and the memory.

7. A printed circuit board on which is mounted a logic device as defined in claim 5.

8. The printed circuit board defined in claim 7 further comprising memory circuitry mounted on the printed circuit board and coupled to the logic device.

9. The printed circuit board defined in claim 7 further comprising processing circuitry mounted on the printed circuit board and coupled to logic device.

10. A programmable logic device comprising:

programmable logic circuitry;

the buffer circuitry defined in claim 1, wherein the input signal is provided to the buffer circuitry by the programmable logic circuitry, and wherein the pair of output signals comprises a first output signal and a second output signal;

first and second interface terminals configured for use in making connections between the programmable logic circuitry and the external circuitry, wherein the buffer circuitry is connected to the first and second interface terminals and configured to selectively provide the first and second interface terminals with the respective first and second output signals; and

input buffer circuitry configured for use in processing first and second input signals that indicate input information by the relative polarities of their voltages, wherein the input buffer circuitry is connected to the first and second interface terminals and configured to selectively receive from the first and second interface terminals the respective first and second input signals for providing a third output signal indicative of the input information to the programmable logic circuitry.

11. A method for receiving an input signal indicative of information and for providing a pair of output signals on a pair of pins that indicate the information by the relative polarity of their voltages comprising:

coupling a first of the two pins to a source of relatively high voltage via first resistor circuitry and coupling a second of the two pins to a source of relatively low voltage via second resistor circuitry when the input signal is at a first logic level;

coupling the second of the two pins to the source of relatively high voltage via the first resistor circuitry and coupling the first of the two pins to the source of relatively low voltage via the second resistor circuitry when the input signal is at a second logic level; and

configuring a transistor in one of the first and second resistor circuitries to increase in resistance in response to an increase in voltage difference between the source of relatively high voltage and the source of relatively low voltage, wherein said transistor is coupled in series with a first resistor and a second resistor.

12. The method of claim 11 further comprising disposing external circuitry in series between the two pins.

13. The method of claim 11 wherein the coupling further comprises using switching circuitry.

14. The method of claim 13 wherein the switching circuitry and the first and second resistor circuitries include transistors, the method further comprising configuring the transistors to have similar changes in resistance due to variations in a manufacturing process for making an integrated circuit including those circuitries.

15. The method of claim 13 wherein the switching circuitry and the first and second resistor circuitries include transistors, the method further comprising configuring the transistors to have similar changes in resistance due to changes in temperature of an integrated circuit including those circuitries.

16. The method of claim 13 further comprising disabling the switching circuitry when it is not desired to provide the pair of output signals.