Programmable reset signal that is independent of supply voltage ramp rate

• US 7,196,561 B2
• Filed: 08/25/2004
• Issued: 03/27/2007
• Est. Priority Date: 08/25/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bhattacharya, Dipankar, Kriz, John C., Loeper, Duane J., Marques, Antonio M.
• Primary Examiner(s): Nguyen; Linh My
• Assistant Examiner(s): Hiltunen; Thomas J.
• Application Number:
  US10/925,613
• Publication Number:
  US 20060044028A1
• Time in Patent Office: 944 Days
• Field of Search: 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.

Claims

1. A power-up reset (PUR) circuit for generating a reset signal, the PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith;

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage; and

a programmable delay circuit having an input for receiving a third control signal and an output for generating the reset signal, the delay circuit being configurable for selectively adjusting a delay between a change of logical state of the second control signal and a change of logical state of the reset signal in response to the third control signal;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.

2. The circuit of claim 1, wherein the programmable delay circuit comprises:

a clock generator;

at least one programmable counter coupled to the clock generator and configured for receiving the third control signal, the programmable counter generating a divide value which is a function of the third control signal; and

control circuitry operatively coupled to the clock generator and to the at least one programmable counter, the control circuitry being operative to generate an output signal having a delay relative to the third control signal, the delay being a function of the divide value;

wherein the reset signal is a function of the output signal from the control circuitry.

3. The circuit of claim 2, further comprising clock enable circuitry operatively coupled to the clock generator and being operative to selectively disable the clock generator as a function of at least one of the second control signal and the output signal generated by the control circuitry.

4. The circuit of claim 2, wherein the clock generator comprises:

a ring oscillator comprising a plurality of inverter stages including first and last stages, the plurality of inverter stages being connected in a ring configuration, such that an output of a given inverter stage is coupled to an input of a successive inverter stage, the output of the last stage being coupled to the input of the first stage; and

a variable delay element connected in series with the plurality of inverter stages, a frequency of the ring oscillator being based at least in part on a delay value of the delay element.

8. The circuit of claim 1, wherein the inverter includes hysteresis configured such that the lower switching point of the inverter is different than an upper switching point of the inverter.

9. The circuit of claim 1, further comprising a passive network coupled to the output of the inverter for setting the output of the inverter to a known logical state at least during a period when the supply voltage is less than the second threshold voltage.

5. A power-up reset (PUR) circuit for generating a reset signal, the PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to the first node, a drain terminal coupled to a fourth node, and a gate terminal coupled to the second node; and

a second resistance element coupled between the third and fourth nodes, the second resistance element having a second resistance value associated therewith;

wherein the second voltage is a function of the first and second resistance values.

6. A power-up reset (PUR) circuit for generating a reset signal, the PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to a fourth node, a drain terminal coupled to a fifth node, and a gate terminal coupled to the second node;

a second resistance element coupled between the third and fifth nodes, the second resistance element having a second resistance value associated therewith; and

a third resistance element coupled between the first and fourth nodes, the third resistance element having a third resistance value associated therewith;

wherein the first voltage is a function of the first threshold voltage and the third resistance value.

7. A power-up reset (PUR) circuit for generating a reset signal, the PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to the first node, a drain terminal coupled to a fourth node, and a gate terminal coupled to the second node;

a second resistance element coupled between the third and fourth nodes, the second resistance element having a second resistance value associated therewith; and

a second transistor including a source terminal coupled to the first node, a drain terminal coupled to the fourth node, and a gate terminal for receiving a third control signal, the third control signal being operative to activate the second transistor when the supply voltage is ramping down and to disable the second transistor otherwise, the second transistor having a threshold voltage which is lower than the first transistor.

10. An integrated circuit including at least one power-up reset (PUR) circuit for generating a reset signal, the at least one PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith;

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage; and

a programmable delay circuit having an input for receiving a third control signal and an output for generating the reset signal, the delay circuit being configurable for selectively adjusting a delay between a change of logical state of the second control signal and a change of logical state of the reset signal in response to the third control signal;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.

11. The integrated circuit of claim 10 wherein the programmable delay circuit comprises:

a clock generator;

at least one programmable counter coupled to the clock generator and configured for receiving the third control signal, the programmable counter generating a divide value which is a function of the third control signal; and

control circuitry operatively coupled to the clock generator and to the at least one programmable counter, the control circuitry being operative to generate an output signal having a delay relative to the third control signal, the delay being a function of the divide value;

wherein the reset signal is a function of the output signal from the control circuitry.

12. The integrated circuit of claim 11, wherein the programmable delay circuit further comprises clock enable circuitry operatively coupled to the clock generator and being operative to selectively disable the clock generator as a function of at least one of the second control signal and the output signal generated by the control circuitry.

13. The integrated circuit of claim 11, wherein the clock generator comprises:

a ring oscillator comprising a plurality of inverter stages including first and last stages, the plurality of inverter stages being connected in a ring configuration, such that an output of a given inverter stage is coupled to an input of a successive inverter stage, the output of the last stage being coupled to the input of the first stage; and

a variable delay element connected in series with the plurality of inverter stages, a frequency of the ring oscillator being based at least in part on a delay value of the delay element.

17. The integrated circuit of claim 10, further comprising a passive network coupled to the output of the inverter for setting the output of the inverter to a known logical state at least during a period when the supply voltage is less than the second threshold voltage.

18. The integrated circuit of claim 11, wherein the inverter includes hysteresis configured such that the lower switching point of the inverter is different than an upper switching point of the inverter.

14. An integrated circuit including at least one power-up reset (PUR) circuit for generating a reset signal, the at least one PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to the first node, a drain terminal coupled to a fourth node, and a gate terminal coupled to the second node; and

a second resistance element coupled between the third and fourth nodes, the second resistance element having a second resistance value associated therewith;

wherein the second voltage is a function of the first and second resistance values.

15. An integrated circuit including at least one power-up reset (PUR) circuit for generating a reset signal, the at least one PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to a fourth node, a drain terminal coupled to a fifth node, and a gate terminal coupled to the second node;

a second resistance element coupled between the third and fifth nodes, the second resistance element having a second resistance value associated therewith; and

a third resistance element coupled between the first and fourth nodes, the third resistance element having a third resistance value associated therewith;

wherein the first voltage is a function of the first threshold voltage and the third resistance value.

16. An integrated circuit including at least one power-up reset (PUR) circuit for generating a reset signal, the at least one PUR circuit comprising:

a first node for receiving a reference voltage and a second node for receiving a supply voltage;

a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node, the voltage level detector including at least a first transistor having a first threshold voltage associated therewith;

a resistance element coupled between the second node and the third node, the resistance element having a first resistance value associated therewith; and

an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal, the inverter including at least a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage;

wherein the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage, the second voltage being less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal;

wherein the voltage level detector comprises;

the first transistor including a source terminal coupled to the first node, a drain terminal coupled to a fourth node, and a gate terminal coupled to the second node;

a second resistance element coupled between the third and fourth nodes, the second resistance element having a second resistance value associated therewith; and

a second transistor including a source terminal coupled to the first node, a drain terminal coupled to the fourth node, and a gate terminal for receiving a third control signal, the third control signal being operative to activate the second transistor when the supply voltage is ramping down and to disable the second transistor otherwise, the second transistor having a threshold voltage which is lower than the first transistor.