Decoupling of analog input and digital output

• US 7,196,644 B1
• Filed: 07/01/2004
• Issued: 03/27/2007
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Anderson, Kent D., Warren, Robert W. Jr., Silvus, Gregory L.
• Primary Examiner(s): Mai; Lam T.
• Application Number:
  US10/883,633
• Time in Patent Office: 999 Days
• Field of Search: 341118-125, 341155-165, 345/100, 345/98, 345/103, 348/189, 348/219
• US Class Current: 341/118
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143

Abstract

A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.

Claims

1. A method comprising:

receiving first and second encoded signals associated with the same information;

sampling the first and second encoded signals;

generating first and second series of digital codes, representative of analog values of each sample of the first and second encoded signals;

storing the first and second series of digital codes in a memory;

computing values that are functions of the first and second series of digital codes; and

storing the computed values into the memory.

2. The method of claim 1, wherein computing values that are functions of the digital codes comprises computing values that are averages of the digital codes in the first and second series of digital codes.

3. The method of claim 1, wherein computing values that are functions of the digital codes comprises computing a series of values wherein each value is a function of one of the digital codes in the first series of digital codes and a corresponding one of the digital codes in the second series of digital codes.

4. The method of claim 3, wherein computing a series of values comprises computing averages of the digital codes in the first series of digital codes and corresponding digital codes in the second series of digital codes.

5. The method of claim 1, further comprising converting the first series of digital codes into a series of binary data bits.

6. The method of claim 5, further comprising detecting errors in the series of binary data bits.