Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power
First Claim
1. A latch circuit for use in a liquid crystal display device, the latch circuit synchronizing a pulse signal for latching image data with a clock signal, comprising:
- a first input terminal into which the pulse signal is inputted, the pulse signal being inputted from the first input terminal to a gate electrode of a first transistor;
a second input terminal into which the clock signal is inputted, the clock signal being inputted from the second input terminal to a gate electrode of a second transistor; and
an output terminal from which a synchronized pulse signal is outputted, wherein the clock signal has an amplitude smaller than an amplitude of the synchronized pulse signal to reduce power consumption.
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Accused Products
Abstract
A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
47 Citations
7 Claims
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1. A latch circuit for use in a liquid crystal display device, the latch circuit synchronizing a pulse signal for latching image data with a clock signal, comprising:
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a first input terminal into which the pulse signal is inputted, the pulse signal being inputted from the first input terminal to a gate electrode of a first transistor; a second input terminal into which the clock signal is inputted, the clock signal being inputted from the second input terminal to a gate electrode of a second transistor; and an output terminal from which a synchronized pulse signal is outputted, wherein the clock signal has an amplitude smaller than an amplitude of the synchronized pulse signal to reduce power consumption. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification