Defect correction of pixel electrode by connection to gate line

• US 7,196,766 B2
• Filed: 02/13/2004
• Issued: 03/27/2007
• Est. Priority Date: 04/08/2003
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Yong-Ho, Yoon, Joo-Sun, Park, Jin-Suk, Choo, Kyo-Seop
• Primary Examiner(s): Schechter; Andrew
• Assistant Examiner(s): Vu; Phu
• Application Number:
  US10/778,693
• Publication Number:
  US 20040201803A1
• Time in Patent Office: 1,138 Days
• Field of Search: 349/114, 349 54- 55, 349/192
• US Class Current: 349/192
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136268 Switch defects
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

In an array substrate and an LCD apparatus having the same, the array substrate includes a signal line, a first insulating layer formed on the signal line, and a pixel electrode formed on the first insulating layer and overlapped with the signal line. The pixel electrode is electrically connected with the signal line so as to discharge a signal through the signal line. A second insulating layer is disposed between the pixel electrode and the first insulating layer, and includes an opening formed in an overlapped area of the pixel electrode and the signal line so as to partially expose the first insulating layer. Thus, the LCD apparatus may have an enhanced display quality.

Claims

1. An array substrate comprising:

a substrate;

a gate signal line formed on the substrate;

a first insulating layer, formed on the substrate and the gate signal line, comprising a first hole formed on the gate signal line;

a second insulating layer, formed on the first insulating layer, comprising an opening which exposes a part of the first insulating layer; and

a plurality of pixel electrodes formed on the first insulating layer and the second insulating layer,

wherein at least one of the pixel electrodes is electrically connected to the gate signal line through the first hole.

2. The array substrate of claim 1, wherein the pixel electrode comprises:

a transmissive electrode; and

a reflective electrode that is formed on the transmissive electrode, and has a transmissive window to expose the transmissive electrode.

3. The array substrate of claim 2, wherein the second insulating layer comprises a thickness in a reflective area on which the reflective electrode is formed thicker than a thickness in a transmissive area at which the transmissive window is formed.

4. The array substrate of claim 3, wherein the gate signal line is formed on the transmissive area, and overlapped with the transmissive electrode.

5. The array substrate of claim 3, wherein the gate signal line is formed on the reflective area, and overlapped with the reflective electrode.

6. The array substrate of claim 3, wherein the second insulating layer comprises a plurality of convex and concave portions formed in the reflective area.

7. The array substrate of claim 6, wherein the pixel electrodes have a plurality of convex and concave portions corresponding to the plurality of convex and concave portions of the second insulating layer.

8. The array substrate of claim 1, further comprising:

a gate line;

a data line substantially perpendicular to the gate line; and

a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.

9. The array substrate of claim 8, wherein the gate signal line is connected to the gate line.

10. The array substrate of claim 1, further compring:

a third insulating layer, formed between the first insulating layer and the second insulating layer, including a second hole aligned with the first hole.

11. The array substrate of claim 1, wherein the pixel electrode is a reflective electrode or a transmissive electrode.

12. A liquid crystal display apparatus comprising:

a first substrate including;

a gate signal line;

a first insulating layer, formed on the first substrate and the gate signal line, comprising a first hole formed on the gate signal line;

a second insulating layer, formed on the first insulating layer, comprising an opening which exposes a part of the first insulating layer; and

a plurality of pixel electrodes formed on the first insulating layer and the second insulating layer;

a second substrate that includes a common electrode comprising a protrusion facing the pixel electrodes on the first insulating layer; and

a liquid crystal layer interposed between the first substrate and the second substrate,

wherein at least one of the pixel electrodes is electrically connected to the gate signal line through the first hole.

13. The LCD apparatus of claim 12, wherein the pixel electrode comprises:

a transmissive electrode; and

a reflective electrode disposed on the transmissive electrode, the reflective electrode having a transmissive window so as to expose the transmissive electrode.

14. The LCD apparatus of claim 13, wherein the second insulating layer comprises a first thickness in a reflective area on which the reflective electrode is formed and a second thickness in a transmissive area at which the transmissive window is formed, and the first thickness is thicker than the second thickness.

15. The LCD apparatus of claim 14, wherein a first distance between the transmissive electrode and the common electrode is larger than a second distance between the reflective electrode and the common electrode.

16. The liquid crystal display apparatus of claim 12, wherein the first substrate further comprises a third insulating layer, formed between the first insulating layer and the second insulating layer, including a second hole aligned with the first hole.

17. An array substrate comprising:

a substrate;

a gate signal line formed on the substrate;

a first insulating layer, formed on the gate signal lines, comprising a first hole formed on the gate signal line;

a second insulating layer, formed on the first insulating layer, comprising an opening which exposes a part of the first insulating layer; and

a plurality of pixel electrodes formed on the first insulating layer and the second insulating layer,

wherein the pixel electrodes comprise a plurality of convex and concave portions, and at least one of the pixel electrodes is electrically connected to the gate signal line through the first hole.

18. The array substrate of claim 17, wherein the pixel electrode comprises:

a transmissive electrode; and

a reflective electrode disposed on the transmissive electrode, and having a transmissive window to expose the transmissive electrode.

19. The array substrate of claim 18, wherein the gate signal line is formed in a transmissive area having the transmissive window, and overlapped with the transmissive electrode.

20. The array substrate of claim 17, wherein the pixel electrode is a reflective electrode or a transmissive electrode.

21. The array substrate of claim 17, further comprising a third insulating layer, formed between the first insulating layer and the second insulating layer, including a second hole aligned with the first hole.

22. The array substrate of claim 17, wherein the first and second insulating layers have a plurality of convex and concave portions corresponding to the plurality of convex and concave portions of the pixel electrodes.