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High-speed verifiable semiconductor memory device

  • US 7,196,933 B2
  • Filed: 12/09/2005
  • Issued: 03/27/2007
  • Est. Priority Date: 12/10/2004
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell storing data using n threshold voltage (n;

    natural number more than

         1);

    a voltage supply circuit supplying a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage; and

    a detection circuit connected to one terminal of the memory cell, the detection circuit charging one terminal of the memory cell to a predetermined potential in the verify operation, detecting a voltage of one terminal of the memory cell at a first detection timing, and detecting a voltage of one terminal of the memory cell at a second detection timing.

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