High-speed verifiable semiconductor memory device

• US 7,196,933 B2
• Filed: 12/09/2005
• Issued: 03/27/2007
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shibata, Noboru
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/297,467
• Publication Number:
  US 20060126392A1
• Time in Patent Office: 473 Days
• Field of Search: 365/185.22, 365/185.03, 365/185.18
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure

Abstract

A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.

Claims

1. A semiconductor memory device comprising:

a memory cell storing data using n threshold voltage (n;

natural number more than

     1);

a voltage supply circuit supplying a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage; and

a detection circuit connected to one terminal of the memory cell, the detection circuit charging one terminal of the memory cell to a predetermined potential in the verify operation, detecting a voltage of one terminal of the memory cell at a first detection timing, and detecting a voltage of one terminal of the memory cell at a second detection timing.

2. The device according to claim 1, wherein a threshold level of the memory cell detected at the first detection timing is higher than a threshold level of the memory cell detected at the second detection timing.

3. The device according to claim 1, wherein the memory cell stores binary or more data.

4. The device according to claim 1, further comprising:

a write circuit supplying a ground potential to one terminal of the memory cell to carry out a write operation with respect to a memory cell whose one terminal has a level lower than the threshold level detected at the second detection timings,

carrying out write wherein a change in threshold voltage is smaller than a change of a threshold voltage by the write operation, with respect to a memory cell whose one terminal has a level higher than the threshold level detected at the second detection timing and lower than the threshold level detected at the first detection timing, and

carrying out no write with respect to a memory cell whose one terminal has a level higher than the threshold level detected at the first detection timing.

5. A semiconductor memory device comprising:

a memory cell storing data using n threshold voltage (n;

natural number more than

     1);

a first data storage circuit connected to one terminal of the memory cell, and storing first or second logic level data inputted externally;

a second data storage circuit connected to one terminal of the memory cell, and storing the first or second logic level data; and

a control circuit connected to the first and second data storage circuits,

the control circuit carrying out the following;

a first operation of stepping up the threshold voltage of the memory cell when the first and second data storage circuits are a first logic level;

a second operation of stepping up the threshold voltage of the memory cell in a range of the threshold voltage less than the first operation when the second data storage circuits is a second logic level;

an operation of charging one terminal of the memory cell while applying a first voltage to a gate of the memory cell in a verify operation of holding the threshold voltage of the memory cell without changing it and verifying whether or not the memory cell reaches a predetermined threshold voltage when the first data storage circuits is a second logic level; and

the first operation in a manner of changing the logic level of the second data storage circuit to a second logic level when the voltage of one terminal of the memory cell is more than a first detection level in a first step, and after predetermined time elapses, changing the logic level of the first data storage circuit to a second logic level when the voltage of one terminal of the memory cell is more than a second detection level in a second step.

6. The device according to claim 5, wherein the first detection level is higher than the second detection level.

7. The device according to claim 5, wherein the control circuit carries out the first and second steps in a manner of charging one terminal of the memory cell while applying a second voltage to a gate of the memory cell like the verify operation in a data read operation.

8. The device according to claim 5, wherein the first voltage supplied to the gate of the memory cell is higher than the second voltage supplied to the gate of the memory cell in read.

9. The device according to claim 5, wherein the first detection level has different value for each memory cell.

10. The device according to claim 5, wherein the first step is carried out at different timing for each memory cell.

11. The device according to claim 5, wherein the control circuit has a counter counting write count, and changes the first detection level when an average value of the write count counted by the counter is more than a predetermined value.

12. The device according to claim 5, wherein the control circuit has a first counter counting write count, and changes a timing of the first step when an average value of the write count counted by the first counter is more than a predetermined value.

13. The device according to claim 5, wherein the other terminal of the memory cell is supplied with a third voltage in the first step, and supplied with a fourth voltage in the second step.

14. The device according to claim 12, wherein a well of the memory cell is supplied with the third voltage in the first step.

15. The device according to claim 13, wherein the third voltage is higher than the fourth voltage.

16. The device according to claim 5, wherein in a verify operation of verifying whether or not the memory cell reaches a threshold voltage, one terminal of the memory cell is charged when the first data storage circuits is a first logic level, while no charge is made when it is a second logic level.

17. The device according to claim 5, wherein the control circuit has a second counter, which counts an erase count of the memory cell and whose count value is stored in the memory cell, and changes the first detection level when the erase count stored in the memory cell is more than a predetermined value.

18. The device according to claim 5, wherein the control circuit has a second counter, which counts an erase count of the memory cell and whose count value is stored in the memory cell, and changes a timing of the first step when the erase count stored in the memory cell is more than a predetermined value.

19. A semiconductor memory device comprising:

a memory storing several data using n threshold voltage (n;

natural number more than

     1);

a first data storage circuit connected to one terminal of the memory cell, and storing first or second logic level data inputted externally; and

a control circuit connected to the first data storage circuit,

the control circuit carrying out a first operation of stepping up the threshold voltage of the memory cell when the first data storage circuits is a first logic level, charging one terminal of the memory cell when the first data storage circuit is a first logic level while applying a first voltage to a gate of the memory cell without making no charge operation when it is second level in a verify operation of holding the threshold voltage of the memory cell without changing it and verifying whether or not the memory cell reaches a predetermined threshold voltage when the first data storage circuits is a second logic level, and making no first operation in a manner of changing the logic level of the first data storage circuit to a second level when the voltage of one terminal of the memory cell is more than a first detection level.

20. A program method of a semiconductor memory device comprising:

carrying out a write operation with respect to a memory cell storing data using different threshold voltage, and making no change of a threshold voltage in a next write operation when the memory cell reaches a predetermined first threshold voltage in a verify operation of and verifying whether or not the memory cell reaches a predetermined first threshold voltage; and

carrying out an i (i;

natural number more than

     3) write operation in the next write operation when the memory cell reaches a voltage lower than the predetermined first threshold voltage, that is, i threshold voltage (i;

natural number more than

     3) (first threshold voltage>

second threshold voltage>

third threshold voltage . . . >

i threshold voltage), and controlling the threshold voltage in the i write operation so that a change becomes small in the order of first threshold voltage<

third threshold voltage<

fourth threshold voltage<

. . . <

k threshold voltage, and repeating the write operation and the verify operation until the memory cell reaches the predetermined first threshold voltage.

21. The method according to claim 20, wherein in the i write operation, a bit line is supplied with i potential (second potential>

third potential>

. . . >

i potential) to carry out write.

22. The method according to claim 21, wherein the predetermined first threshold voltage includes several threshold voltages to store several data.

23. A semiconductor memory device comprising:

a memory cell array having several memory cells arrayed like a matrix, which are connected to a word line and a bit line and store n value (n;

natural number more than

     3); and

a control circuit controlling each potential of the word line and the bit line in accordance with input data, and writing data in the memory cell,

the control circuit carrying out write using k value (k<

=n) in the write operation,

charging the bit line, and thereafter, changing the word line potential m times to verify whether or not the memory cell reaches a normal m threshold value (m<

=k), and

charging the bit line in j value (j<

=n) data read, and thereafter, changing a voltage supplied to the word line m times same as the verify operation to carry out a read operation.

24. A semiconductor memory device comprising:

a memory cell array having several memory cells arrayed like a matrix, which are connected to a word line and a bit line and store n value (n;

natural number more than

     3); and

a control circuit controlling each potential of the word line and the bit line in accordance with input data, and writing data in the memory cell,

the control circuit carrying out write using k value (k<

=n) in the write operation, and charging the bit line, thereafter, changing the word line potential m times to verify whether or not the memory cell reaches a normal m threshold value (m<

=k),

charging the bit line again, thereafter, changing the word line potential m times to verify whether or not the memory cell reaches a normal m threshold value (m<

=k), and in the next write operation, making a write speed late when the memory cell reaches the normal m threshold value while carrying out no write operation when it reaches the normal m threshold value.

25. The method according to claim 24, further comprising:

charging the bit line in j value (j<

=n) data read, and thereafter, changing a voltage supplied to the word line m times same as the verify operation to carry out a read operation.

26. A semiconductor memory device comprising:

a memory cell array storing n value (n;

natural number more than

     2), and having at least one first memory cell arrayed like matrix and at least one second memory cell selected simultaneously with the first memory cell,

the memory cell array outputting data of the first memory cell when a logic level of the second memory cell is a first logic level, and outputting output data of the first memory cell as a fixed value when the logic level of the second memory cell is a second logic level.