Non-volatile semiconductor storage device performing ROM read operation upon power-on
First Claim
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1. A data read method for a semiconductor device having a plurality of independently-controllable ROM regions comprising:
- inputting a read command and a read address after a power supply voltage is applied, the read command and read address including information that corresponds to one of the ROM regions; and
reading data out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input,wherein the independently-controllable ROM regions are 2n (where n is a natural number) in number, and the semiconductor device includes n pads so as to specify the information corresponding to one of the ROM regions.
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Abstract
A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.
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Citations
13 Claims
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1. A data read method for a semiconductor device having a plurality of independently-controllable ROM regions comprising:
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inputting a read command and a read address after a power supply voltage is applied, the read command and read address including information that corresponds to one of the ROM regions; and reading data out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input, wherein the independently-controllable ROM regions are 2n (where n is a natural number) in number, and the semiconductor device includes n pads so as to specify the information corresponding to one of the ROM regions. - View Dependent Claims (2, 3, 4)
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5. A data read method for a semiconductor device having a plurality of independently-controllable ROM regions comprising:
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inputting a read command and a read address after a power supply voltage is applied, the read command and read address including information that corresponds to one of the ROM regions; and reading data out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input, wherein each of the ROM regions includes a delay circuit, and data is read out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input and after lapse of a delay time provided by a delay circuit corresponding to the ROM region specified by the information included in the read command and read address. - View Dependent Claims (6, 7, 8, 9)
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10. A data read method for a semiconductor device having a plurality of independently-controllable ROM regions comprising:
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inputting a read command and a read address after a power supply voltage is applied, the read command and read address including information that corresponds to one of the ROM regions; and reading data out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input, wherein each of the ROM regions are included in a NAND flash memory. - View Dependent Claims (11, 12, 13)
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Specification