Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

• US 7,197,575 B2
• Filed: 01/10/2003
• Issued: 03/27/2007
• Est. Priority Date: 12/17/1997
• Status: Expired due to Fees

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Huppenthal, Jon M., Burton, Lee A., Seeman, Thomas R.
• Primary Examiner(s): Huynh; Kim
• Assistant Examiner(s): Sorrell; Eron
• Application Number:
  US10/340,390
• Publication Number:
  US 20050076152A1
• Time in Patent Office: 1,537 Days
• Field of Search: 709/230, 709/236, 709/237, 709/246, 709/250, 710 62- 66, 710/105, 370463-476
• US Class Current: 709/250
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Claims

1. A computer system comprising:

at least one processor;

a controller for coupling said at least one processor to a control block and a memory bus;

a plurality of memory module slots coupled to said memory bus;

an adapter port associated with a subset of said plurality of memory module slots; and

a cluster interconnect fabric coupled to said adapter port,

wherein control information from or to said controller via a relatively low speed bus to or from said adapter port is provided by a direct connection between card slots associated with said relatively low speed bus and said plurality of memory module slots.

2. The computer system of claim 1 wherein said controller comprises an interleaved memory controller.

3. The computer system of claim 1 wherein said plurality of memory module slots comprise DIMM memory module slots.

4. The computer system of claim 3 wherein said adapter port comprises a DIMM physical format for retention within one of said DIMM memory module slots.

5. The computer system of claim 1 wherein said plurality of memory module slots comprise high speed serialized memory interconnect format memory module slots.

6. The computer system of claim 5 wherein said adapter port comprises a high speed serialized memory interconnect physical format.

7. The computer system of claim 1 wherein said control block comprises a peripheral bus control block.

8. The computer system of claim 1 wherein said control block comprises a graphics control block.

9. The computer system of claim 1 wherein said control block comprises a systems maintenance control block.

10. The computer system of claim 1 wherein said adapter port comprises:

a memory bus data multiplexer adapted to receive data information from said memory bus.

11. The computer system of claim 10 wherein said adapter port further comprises:

an address and command decoder adapted to receive address information from said memory bus.

12. The computer system of claim 11 further comprising:

a command formatter coupling said address and command decoder to a processor element coupled to said cluster interconnect fabric.

13. The computer system of claim 10 wherein said adapter port further comprises:

a write buffer for coupling said data information received from said memory bus to a processor element coupled to said cluster interconnect fabric; and

a read buffer for coupling data provided by said processor element to said memory bus.

14. The computer system of claim 13 further comprising:

a packetizer for coupling said write buffer to said processor element; and

a depacketizer for coupling said processor element to said read buffer.

15. The computer system of claim 10 further comprising:

a plurality of registers coupled to said memory bus data multiplexer.

16. The computer system of claim 15 wherein said plurality of registers comprise configuration registers.

17. The computer system of claim 15 wherein said plurality of registers comprise status registers.

18. The computer system of claim 1 further comprising a reconfigurable processor element coupled to said cluster interconnect fabric.

19. The computer system of claim 1 further comprising a processor element coupled to said cluster interconnect fabric operative to alter data received from said controller on said memory bus.

20. The computer system of claim 1 further comprising a processor element coupled to said cluster interconnect fabric operative to alter data received from an external source prior to placing altered data on said memory bus.

21. The computer system of claim 1 further comprising a control block coupled to said cluster interconnect fabric.

22. The computer system of claim 21 wherein said control block further comprises:

at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.

23. The computer system of claim 22 further comprising:

a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.

24. The computer system of claim 21 wherein said control block further comprises:

a read only memory for providing configuration information thereto.

25. The computer system of claim 1 further comprising a chain port coupled to said cluster interconnect fabric.

26. The computer system of claim 1 further comprising a processor element coupled to said cluster interconnect fabric.

27. A computer system comprising:

at least one processor;

an interleaved controller for coupling said at least one processor to a control block and a memory bus;

a plurality of memory slots coupled to said memory bus;

an adapter port associated with at least two of said plurality of memory slots; and

a cluster interconnect fabric coupled to each of said adapter ports,

wherein control information from or to said controller via a relatively low speed bus to or from said adapter port is provided by a direct connection between card slots associated with said relatively low speed bus and said plurality of memory module slots.

28. The computer system of claim 27 wherein said plurality of memory slots comprise DIMM memory module slots.

29. The computer system of claim 28 wherein said adapter port comprises a DIMM physical format for retention within one of said DIMM memory module slots.

30. The computer system of claim 27 wherein said plurality of memory slots comprise high speed serialized memory interconnect format memory module slots.

31. The computer system of claim 30 wherein said adapter port comprises a high speed serialized memory interconnect physical format.

32. The computer system of claim 27 wherein said control block comprises a peripheral bus control block.

33. The computer system of claim 27 wherein said control block comprises a graphics control block.

34. The computer system of claim 27 wherein said control block comprises a systems maintenance control block.

35. The computer system of claim 27 wherein said adapter port comprises:

a memory bus data multiplexer adapted to receive data information from said memory bus.

36. The computer system of claim 35 wherein said adapter port further comprises:

an address and command decoder adapted to receive address information from said memory bus.

37. The computer system of claim 36 further comprising:

a command formatter coupling said address and command decoder to a processor element coupled to said cluster interconnect fabric.

38. The computer system of claim 35 wherein said adapter port further comprises:

a write buffer for coupling said data information received from said memory bus to a processor element coupled to said cluster interconnect fabric; and

a read buffer for coupling data provided by said processor element to said memory bus.

39. The computer system of claim 38 further comprising:

a packetizer for coupling said write buffer to said processor element; and

a depacketizer for coupling said processor element to said read buffer.

40. The computer system of claim 35 further comprising:

a plurality of registers coupled to said memory bus data multiplexer.

41. The computer system of claim 40 wherein said plurality of registers comprise configuration registers.

42. The computer system of claim 40 wherein said plurality of registers comprise status registers.

43. The computer system of claim 27 further comprising a reconfigurable processor element coupled to said duster interconnect fabric.

44. The computer system of claim 27 further comprising a processor element coupled to said duster interconnect fabric operative to alter data received from said controller on said memory bus.

45. The computer system of claim 27 further comprising a processor element coupled to said duster interconnect fabric operative to alter data received from an external source prior to placing altered data on said memory bus.

46. The computer system of claim 27 further comprising a control block coupled to said cluster interconnect fabric.

47. The computer system of claim 46 wherein said control block further comprises:

at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.

48. The computer system of claim 47 further comprising:

a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.

49. The computer system of claim 46 wherein said control block further comprises:

a read only memory for providing configuration information thereto.

50. The computer system of claim 27 further comprising a chain port coupled to said cluster interconnect fabric.

51. The computer system of claim 27 further comprising a processor element coupled to said cluster interconnect fabric.