Circuit, system and method for encoding data to be stored on a non-volatile memory array

• US 7,197,594 B2
• Filed: 09/23/2003
• Issued: 03/27/2007
• Est. Priority Date: 09/23/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Infineon Technologies AG
• Inventors: Marcu, Alon, Cohen, Zeev, Raz, Meirav
• Primary Examiner(s): Sough; Hyung
• Assistant Examiner(s): Song; Jasmine
• Application Number:
  US10/667,481
• Publication Number:
  US 20050066110A1
• Time in Patent Office: 1,281 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation

Abstract

The present invention is a method, circuit and system for storing bits on a Non-Volatile Memory (“NVM”) array. According to some embodiments of the present invention, a bit scrambling block may rearrange the received block of bits according to a spreading pattern. An error correction code block may generate an error correction code (“ECC”) based on either the original block of bits or based on the rearranged block of bits, and a data storing circuit may store in the NVM array the ECC and the block of bits from which the ECC was not derived.

Claims

1. A control circuit for storing bits of a data block on a Non-Volatile Memory (“

NVM”

) array, said circuit comprising;

a bit scrambling block adapted to rearrange the bit of the data block according to a spreading pattern;

an Error Correction Coding (“

ECC”

) block adapted to generate an ECC based on either the original data block or on the rearranged data block;

an NVM storing circuit adapted to store in said NVM array the ECC and the block of bits from which the ECC was not derived;

a reading circuit adapted to read a stored block of bits from the NVM array;

wherein said bit scrambling block is adapted to scramble the read data block if the block was stored unscrambled; and

wherein the ECC block is adapted to manipulate the scrambled block according to an ECC which is based on a scrambled version of the original data block prior to being stored on the NVM.

2. The control circuit according to claim 1, further comprising a de-scrambler adapted to rearrange a block of bits stored according to spreading pattern.

3. The control circuit according to claim 2, wherein the ECC block is adapted to manipulate the de-scrambled block of data according to an ECC which is based on the original data block prior to scrambling.