Computer arrangement using non-refreshed DRAM

• US 7,197,596 B2
• Filed: 02/02/2006
• Issued: 03/27/2007
• Est. Priority Date: 12/06/1999
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: De Jong, Eduard Karel
• Primary Examiner(s): Nguyen; Hiep T.
• Application Number:
  US11/345,519
• Publication Number:
  US 20060129756A1
• Time in Patent Office: 418 Days
• Field of Search: 711/105, 711/106, 365/222
• US Class Current: 711/105
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52

Abstract

A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangement is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.

Claims

1. A terminal provided with a terminal processor and a terminal communication interface connected to said terminal processor and arranged for communicating with a computer arrangement comprising a processor, a communication interface and at least one memory unit, said communication interface and said at least one memory unit being connected to said processor, said at least one memory unit comprising memory for storing a computer program with a predetermined sequence of instructions and dynamic random access memory, said computer arrangement being arranged to use but not to refresh at least part of said dynamic random access memory while running said program, wherein said terminal processor is arranged to carry out the following steps:

(a) emulating said computer program;

(b) analyzing time period necessary for the processor of the computer arrangement to carry out each instruction of said sequence of instructions and determining all retention times necessary for the processor to temporarily store data in said at least part of said dynamic random access memory during carrying out said sequence of instructions;

(c) establishing sets of consecutive instructions for which said retention times are longer than a predetermined refresh time

(d) adding additional instructions to said sets of consecutive instructions in order to obtain modified retention times of those sets of consecutive instructions which modified retention times are shorter than said predetermined refresh times.

2. The terminal of claim 1, wherein adding additional instructions includes:

adding read and write instructions to the sets of consecutive instructions.

3. A method for processing instructions using a Dynamic Random Access Memory (DRAM), comprising:

providing a DRAM having a word line of memory cells including a set of witness cells;

running a program by a processor that writes data into the word line of the DRAM, the processor arranged to use but not to refresh at least part of the DRAM while running the program,

writing a predetermined data pattern in the witness cells in response to the processor writing the data into the word line of the DRAM;

reading data from the witness cells in response to a determination that the processor reads data from the word line;

comparing the data read from the witness cells to the predetermined data pattern; and

preventing execution of the program when the witness cell data does not match the predetermined data pattern.

4. The method of claim 3, further including:

continuing execution of the program when the witness cell data matches the predetermined data pattern.

5. The method of claim 3, further including:

testing the word line to identify a memory cell having a shortest data retention time in relation to other memory cells of the word line; and

designating the memory cell having the shortest data retention time as a witness cell.

6. The method of claim 3, further including:

providing the processor and DRAM on a smart card.

7. A method for processing a software program including instructions for execution by a processor that uses a Dynamic Random Access Memory (DRAM), comprising:

determining a corresponding time period for the processor to execute each instruction of the software program;

determining a corresponding time period between updates of data stored in the DRAM and used by the software program instructions when executed by the processor;

determining a set of instructions in the software program that require data to be retained in the DRAM longer than a retention time of the DRAM, wherein the retention time is a period of time that data is retained in the DRAM when no refresh operation is used; and

rearranging the determined set of instructions to ensure data stored in the DRAM is used the software program instructions before the end of the retention time of the DRAM.

8. The method of claim 7, wherein rearranging the determined set of instructions includes at least one of:

unrolling program loops in the set of instructions; and

adding instructions to the set of instructions.

9. The method of claim 8, wherein adding instructions includes:

adding read and write instructions to the set of instructions to perform an artificial refresh operation of data used by the set of instructions.

10. The method of claim 7, wherein the processor and DRAM are each located within a smart card.

11. A system for processing instructions using a Dynamic Random Access Memory (DRAM), comprising:

a DRAM having a word line of memory cells including a set of witness cells;

a processor that executes a program that writes data into the word line of the DRAM, the processor arranged to use but not to refresh at least part of the DRAM while executing the program, and

a logic component configured to compare data stored in the set of witness cells to a predetermined data pattern previously written into the set of witness cells, and provide an indication to the processor when the logic determines the stored witness cell data does not match the predetermined data pattern,

wherein the processor is configured to prevent further execution of the program in response to receiving the indication.

12. The system of claim 11, wherein the processor is configured to continue execution of the program when no indication is received from the logic.

13. The system of claim 11, wherein the predetermined data pattern is written into the set of witness cells when the processor writes data in the word line.

14. The system of claim 11, wherein the processor is configured to read the data stored in the set of witness cells when the processor reads data stored in the word line.

15. The system of claim 11, further including a second processor that is configured to read the data stored in the set of witness cells when the processor reads data stored in the word line.

16. The system of claim 11, wherein the logic component is configured as part of the processor.

17. The system of claim 11, wherein the set of witness cells are designed such that their data retention time is significantly shorter than the data retention times of other memory cells in the word line.

18. The system of claim 11, wherein the word line is previously tested to identify a set of memory cells having a shortest data retention time in relation to other memory cells of the word line, and wherein the identified set of memory cells having the shortest data retention time are used as the set of witness cells.

19. The system of claim 11, wherein the system is a smart card.

21. The system of claim 18, wherein the second processor rearranges the determined set of instructions by at least one of:

unrolling program loops in the set of instructions; and

adding new instructions to the set of instructions.

22. The system of claim 19, wherein the second processor is configured to add read and write instructions to the set of instructions to perform an artificial refresh operation of data used by the set of instructions.

23. The system of claim 18, wherein the processor and DRAM are each located within a smart card.

20. A system for processing a software program including instructions, comprising:

a first processor that executes the software program and uses a Dynamic Random Access Memory (DRAM); and

a second processor configured to;

determine a corresponding time period for the first processor to execute each instruction of the software program,

determine a corresponding time period between updates of stored data in the DRAM used by the software program instructions when executed by the first processor,

determine a set of instructions in the software program that require data to be retained in the DRAM longer than a retention time of the DRAM, wherein the retention time is a period of time that data is retained in the DRAM when no refresh operation is used, and

rearrange the determined set of instructions to ensure data stored in the DRAM is used the software program instructions before the end of the retention time of the DRAM.

24. A terminal comprising:

a terminal processor; and

a first interface that communicates with a second interface included on a separate computer arrangement including a DRAM having a word line of memory cells including a set of witness cells, a processor that executes a program that writes data into the word line of the DRAM, the processor arranged to use but not to refresh at least part of the DRAM while executing the program, and a logic component configured to compare data stored in the set of witness cells to a predetermined data pattern previously written into the set of witness cells, and provide an indication to the processor when the logic component determines the stored witness cell data does not match the predetermined data patter, wherein the processor prevents further execution of the program in response to receiving the indication.