Plural microcontrollers for managing CPU allocation and device resources including establishing connections without a centralized operating system
First Claim
1. A computer system for use with a device, the system comprising:
- a central processing unit (CPU);
a main memory;
at least one device interface configured to be coupled to the device and to receive process requests from the device;
a further unit comprising;
a first microcontroller module;
a first memory containing a first set of instructions configured to cause the first microcontroller module to manage CPU operations and to cause the first microcontroller to allocate CPU resources to each of the process requests received by the at least one device interface;
a second microcontroller module in communication with the first microcontroller and configured to receive the process requests from the at least one device interface;
a second memory containing a second set of instructions configured to cause the second microcontroller module to manage the device, and to identify the device and a means of connection used by the device;
a third microcontroller module in communication with the first microcontroller;
a third memory containing a third set of instructions configured to cause the third microcontroller module to manage memory operations;
a fourth microcontroller module in communication with the first microcontroller;
a fourth memory containing a fourth set of instructions configured to cause the fourth microcontroller module to manage data operations,wherein the CPU and the further unit both reside on a motherboard; and
a plurality of trace links connecting the further unit to the CPU, the main memory, and the device interface to facilitate communication between the further unit, the CPU, the main memory, and the device.
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Abstract
A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device.
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Citations
16 Claims
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1. A computer system for use with a device, the system comprising:
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a central processing unit (CPU); a main memory; at least one device interface configured to be coupled to the device and to receive process requests from the device; a further unit comprising; a first microcontroller module; a first memory containing a first set of instructions configured to cause the first microcontroller module to manage CPU operations and to cause the first microcontroller to allocate CPU resources to each of the process requests received by the at least one device interface; a second microcontroller module in communication with the first microcontroller and configured to receive the process requests from the at least one device interface; a second memory containing a second set of instructions configured to cause the second microcontroller module to manage the device, and to identify the device and a means of connection used by the device; a third microcontroller module in communication with the first microcontroller; a third memory containing a third set of instructions configured to cause the third microcontroller module to manage memory operations; a fourth microcontroller module in communication with the first microcontroller; a fourth memory containing a fourth set of instructions configured to cause the fourth microcontroller module to manage data operations, wherein the CPU and the further unit both reside on a motherboard; and a plurality of trace links connecting the further unit to the CPU, the main memory, and the device interface to facilitate communication between the further unit, the CPU, the main memory, and the device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computer system for use with a device, the system comprising:
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a central processing unit (CPU); a main memory; an interface configured to be coupled to the device and to receive process requests from the device; a further unit comprising; a first microcontroller module having firmware that contains a first set of instructions configured to cause the microcontroller to manage CPU operations and to cause the first microcontroller module to allocate CPU resources to each of the process requests received by the interface, a second microcontroller module in communication with the first microcontroller and configured to receive the process requests from the interface, the second microcontroller module having firmware that contains a second set of instructions configured to cause the second microcontroller to manage the device and to identify the device and a means of connection used by the device; a third microcontroller module in communication with the first microcontroller and having firmware that contains a third set of instructions configured to cause the third microcontroller to manage memory operations; a fourth microcontroller module in communication with the first microcontroller and having firmware that contains a fourth set of instructions configured to cause the fourth microcontroller to manage data operations, and a plurality of trace links connecting the further unit to the CPU, the main memory, and to the interface for the device to facilitate communication between the further unit, the CPU, the main memory, and the device. - View Dependent Claims (13, 14, 15, 16)
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Specification