Lowered PU power usage method and apparatus

• US 7,197,655 B2
• Filed: 06/26/2003
• Issued: 03/27/2007
• Est. Priority Date: 06/26/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Liberty, John Samuel, Hofstee, Harm Peter, Flachs, Brian King
• Primary Examiner(s): Browne; Lynne H.
• Assistant Examiner(s): Sugent; James F.
• Application Number:
  US10/606,581
• Publication Number:
  US 20040268164A1
• Time in Patent Office: 1,370 Days
• Field of Search: 713300-340
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections

Abstract

Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.

Claims

1. A computer system, comprising:

a channel unit comprising a counter corresponding to a data channel;

a processor coupled to receive computer program instructions and a power control signal, wherein the processor is configured to execute the received computer program instructions, and wherein the processor comprises at least one component that is not used when the processor has executed all received computer program instructions and is waiting for further computer program instructions, and wherein the processor is configured to transition the at least one component to a low power mode in response to the power control signal;

means for decrementing a count stored in the counter when the processor executes an instruction corresponding to the data channel;

means for producing the power control signal in the event the count stored in the counter reaches a predetermined value;

wherein the channel unit is configured to decrement the count stored in the counter when the processor executes an instruction corresponding to the data channel; and

wherein the processor is configured to provide a signal to the channel unit in the event an instruction corresponding to the data channel is executed, and wherein the channel unit is configured to produce a wait signal in the event the count stored in the counter reaches the predetermined value.

2. The computer system as recited in claim 1, further comprising an instruction issue unit coupled to receive computer program instructions and the wait signal produced by the channel unit, wherein the instruction issue unit is configured to provide the computer program instructions to the processor and to respond to the wait signal by producing the power control signal.

3. A computer system, comprising:

a channel unit coupled to receive an external channel event signal corresponding to a data channel, wherein the channel unit comprises a counter corresponding to the data channel, and wherein the channel unit is configured to produce a wait signal;

an instruction issue unit coupled to receive computer program instructions and the wait signal produced by the channel unit, wherein the instruction issue unit is configured to provide the computer program instructions and to produce a power control signal;

a processor coupled to the channel unit and to receive the computer program instructions and the power control signal from the instruction issue unit, wherein the processor is configured to execute the received computer program instructions;

wherein the processor is configured to provide a signal to the channel unit in the event an instruction corresponding to the data channel is executed;

wherein the channel unit is configured to respond to the signal from the processor by decrementing a count stored in the counter, and to produce the wait signal in the even the count reaches a predetermined value;

wherein the instruction issue unit is configured to respond to the wait signal by producing the power control signal;

wherein the processor comprises at least one component that is not used when the processor has executed all received computer program instructions and is waiting for further computer program instructions; and

wherein the processor is configured to respond to the power control signal from the instruction issue unit by transitioning the at least one component to a low power mode.

4. The computer system as recited in claim 3, wherein the channel unit is configured to produce the wait signal in the event the count stored in the counter is a predetermined minimum value corresponding to a predetermined minimum amount of data in the data channel.

5. The computer system as recited in claim 3, wherein the channel unit is configured to produce the wait signal in the event the count stored in the counter is a predetermined maximum value corresponding to a predetermined maximum amount of data in the data channel.

6. The computer system as recited in claim 3, wherein the at least one component that is not used when the processor has executed all received computer program instructions and is waiting for further computer program instructions comprises a fixed point math unit, a branch unit, an instruction decode unit, an instruction storage unit, a load/store unit, or a floating point math unit.

7. The computer system as recited in claim 3, wherein the channel unit is configured to respond to the external channel event signal by incrementing the count stored in the counter.

8. A computer system, comprising:

a channel unit coupled to receive an external channel event signal corresponding to a blocking channel of a plurality of data channels, and wherein the channel unit comprises a plurality of counters each corresponding to a different one of the data channels, and wherein the channel unit is configured to produce a wait signal;

an instruction issue unit coupled to receive computer program instructions of an instruction set and the wait signal produced by the channel unit, wherein the instruction issue unit is configured to provide the computer program instructions and to produce a power control signal;

a processor coupled to the channel unit and to receive the computer program instructions and the power control signal from the instruction issue unit, wherein the processor is configured to execute the received computer program instructions;

wherein the processor is configured to provide a signal to the channel unit in the event an instruction corresponding to one of the data channels is executed;

wherein the channel unit is configured to respond to the signal from the processor by decrementing a count stored in the counter corresponding to the data channel, and to produce the wait signal in the event the count corresponding to the blocking channel is a predetermined value;

wherein the instruction issue unit is configured to respond to the wait signal by producing the power control signal;

wherein the processor comprises at least one component that is not used when the processor has executed all received computer program instructions and is waiting for further computer program instructions; and

wherein the processor is configured to respond to the power control signal from the instruction issue unit by transitioning the at least one component to a low power mode.

9. The computer system as recited in claim 8, wherein each of the data channels is assigned a different channel number, and wherein each of the computer program instructions corresponds to one of the data channels and comprises the channel number of the corresponding data channel.

10. The computer system as recited in claim 8, wherein the signal provided by the processor to the channel unit when a computer program instruction is executed comprises the channel number of the corresponding data channel.

11. The computer system as recited in claim 10, wherein the channel unit is configured to respond to the signal from the processor by decrementing the count stored in the counter corresponding to the data channel having the channel number.

12. The computer system as recited in claim 8, wherein the channel unit is configured to produce the wait signal in the event the count stored in the counter corresponding to the blocking channel is a predetermined minimum value corresponding to a predetermined minimum amount of data in the blocking channel.

13. The computer system as recited in claim 8, wherein the channel unit is configured to produce the wait signal in the event the count stored in the counter corresponding to the blocking channel is a predetermined maximum value corresponding to a predetermined maximum amount of data in the blocking channel.

14. The computer system as recited in claim 8, wherein the channel unit is configured to respond to the external channel event signal by incrementing the count stored in the counter corresponding to the blocking channel.

15. The computer system as recited in claim 8, wherein the instruction set comprises a channel read operation instruction, and wherein the channel read operation instruction comprises a channel number and identifies a register of the processor where data of the data channel having the channel number is to be stored.

16. The computer system as recited in claim 8, wherein the instruction set comprises a channel write operation instruction, and wherein the channel write operation instruction comprises a channel number and identifies a register of the processor where data of the data channel having the channel number is to be obtained.