Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM)

• US 7,197,670 B2
• Filed: 12/31/2003
• Issued: 03/27/2007
• Est. Priority Date: 12/31/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Scafidi, Carl, Boatright, Bryan D., Shirley, C. Glenn, Eapen, Ben J.
• Primary Examiner(s): Maskulinski; Michael C.
• Application Number:
  US10/750,562
• Publication Number:
  US 20050160326A1
• Time in Patent Office: 1,182 Days
• Field of Search: 714/42, 711/144, 711/145
• US Class Current: 714/42
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

In accordance with various embodiments of the present invention, a cache-equipped semi-conductor device is provided with enhanced error detection logic to detect a first location-independent error within an area of the cache memory and prevent further use of the area if the error is determined to be the second consecutive error associated with a common area.

Claims

1. A method comprising:

detecting an error within a cache line of a cache memory;

determining whether the error is a second consecutive error associated with the cache line; and

preventing further use of the cache line if the error is determined to be the second consecutive error associated, with the cache line by modifying a cache management system to at least inhibit subsequent access to the cache line, said modifying including at least a selected one of modifying by the cache management system a value corresponding to a particular set such that the cache line is less likely to be accessed than at least one other cache line, and assigning by the cache management system a disable state to the cache line as part of a MESI state assignment.

2. The method of claim 1, wherein the cache memory comprises an n-way set associative static random access memory.

3. The method of claim 2, wherein the error comprises an error checking and correcting (ECC) based error.

4. The method of claim 1, further comprising:

comparing a current operation address corresponding to the error with a stored address corresponding to a previous error; and

identifying the error as the second consecutive error if the current operation address matches the stored address.

5. The method of claim 4, further comprising:

storing the current operation address corresponding to the error in place of the stored address corresponding to the previous error if the current operation address does not match the stored address.

6. The method of claim 5, further comprising:

accessing the current operation address corresponding to the error a second time to determine whether the second consecutive error occurs.

7. The method of claim 1, further comprising:

determining whether data stored in the cache line of the cache memory has been modified as compared to data stored in a corresponding area of main memory;

facilitating recovery of the modified data stored in the area of the cache memory; and

preventing further use of the cache line of the cache memory after the modified data stored in the cache line of cache memory has been recovered.

8. The method of claim 1, wherein the error is detected via programmable built-in self test (PBIST) logic.

9. A processor comprising:

a cache memory;

error detection logic coupled to the cache memory, the error detection logic equipped to;

detect an error within a cache line of the cache memory;

determine whether the error is a second consecutive error associated with the cache line; and

prevent further use of the cache line if the error is determined to be the second consecutive error associated with the cache line by modifying a cache management system to at least inhibit subsequent access to the cache line, said modifying including at least a selected one of modifying by the cache management system a value corresponding to a particular set such that the cache line is less likely to be accessed than at least one other cache line, and assigning a disable state to the cache line as part of a MESI state assignment.

10. The processor of claim 9, wherein the cache memory comprises an n-way set associative static random access memory (SRAM).

11. The processor of claim 9, wherein the error detection logic comprises:

error checking and correcting logic to detect an error within the cache memory;

hard error detection logic to determine whether the detected error is a hard error; and

cacheline disable logic to disable a cache line affected by the error if it is determined that the detected error is a hard error.

12. The processor of claim 11, wherein the hard error detection logic further comprises:

an error register to store address information indicating at least the cache line affected by the error;

comparison logic to compare stored address information with a current operating address; and

state logic to determine whether the error is a second consecutive error based upon output from the comparison logic.

13. The processor of claim 12, wherein the cacheline disable logic further comprises:

a decoder to generate a way-disable vector prevent further use of the cache line; and

way-select logic to select the cache line to be disabled based upon the way-disable vector;

wherein the way-disable vector operates to modify a cache management system including at least one of a least recently used (LRU) algorithm and a MESI protocol.

14. The processor of claim 9, further comprising programmable built-in self test (PBIST) logic coupled to the error detection logic to facilitate detection of the error during a startup routine of the processor.

15. A system comprising:

a dynamic random access memory and;

an integrated circuit coupled to the dynamic random access memory, the integrated circuit including a cache memory and error detection logic, wherein the error detection logic is equipped to;

detect an error within a cache line of the cache memory,

determine whether the error is a second consecutive error associated with the cache line, and

prevent further use of the cache line if the error is determined to be the second consecutive error associated with the cache line by modifying a cache management system to at least inhibit subsequent access to the cache line, said modifying including at least a selected one of modifying a value corresponding to a particular set such that the cache line is less likely to be accessed than at least one other cache line, and assigning a disable state to the cache line as part of a MESI state assignment.

16. The system of claim 15, wherein the integrated circuit further includes a central processing unit and at least one input/output module coupled to the central processor unit.

17. The system of claim 15, wherein the integrated circuit is a microprocessor.