Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps
First Claim
1. An apparatus,a data partitioner that is operable to partition a plurality of input bits into a first plurality of input bits and a second plurality of input bits;
- a first LDPC (Low Density Parity Check) encoder that is operable to encode the first plurality of input bits thereby generating a first level LDPC codeword;
a second LDPC encoder that is operable to encode the second plurality of input bits thereby generating a second level LDPC codeword;
a symbol mapper that is operable to;
group at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols;
group at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols;
symbol map the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings;
symbol map the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings; and
output an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal, being a sequence of discrete-valued modulation symbols that is mapped using a plurality of mappings, that includes the symbol mapped first sub-block symbol and the symbol mapped second sub-block symbol.
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Abstract
Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon'"'"'s limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.
51 Citations
23 Claims
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1. An apparatus,
a data partitioner that is operable to partition a plurality of input bits into a first plurality of input bits and a second plurality of input bits; -
a first LDPC (Low Density Parity Check) encoder that is operable to encode the first plurality of input bits thereby generating a first level LDPC codeword; a second LDPC encoder that is operable to encode the second plurality of input bits thereby generating a second level LDPC codeword; a symbol mapper that is operable to; group at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols; group at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols; symbol map the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings; symbol map the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings; and output an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal, being a sequence of discrete-valued modulation symbols that is mapped using a plurality of mappings, that includes the symbol mapped first sub-block symbol and the symbol mapped second sub-block symbol. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. The apparatus, comprising:
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a data partitioner that is operable to partition a plurality of input bits into a first plurality of input bits and a second plurality of input bits; a first LDPC (Low Density Parity Check) encoder that is operable to encode the first plurality of input bits using a first code rate LDPC code thereby generating a first level LDPC codeword; a second LDPC encoder that is operable to encode the second plurality of input bits using a second code rate LDPC code thereby generating a second level LDPC codeword; a symbol mapper that is operable to; group at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols; group at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols; symbol map the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings; symbol map the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings; and output an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal, being a sequence of discrete-valued modulation symbols that is mapped using a plurality of mappings, that includes the symbol mapped first sub-block symbol and the symbol mapped second sub-block symbol; a clock counter that is operable to provide a clock signal having clock cycles; a map selector that is operable to; receive the clock signal from the clock counter; provide a first selected mapping to the symbol mapper during a first clock cycle of the clock signal; provide a second selected mapping to the symbol mapper during a second clock cycle of the clock signal; and wherein the symbol mapper is operable to employ at least one of the first selected mapping and the second selected mapping as at least one of the first mapping of the plurality of mappings and the second mapping of the plurality of mappings.
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13. A method, comprising:
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partitioning a plurality of input bits into a first plurality of input bits and a second plurality of input bits; encoding the first plurality of input bits thereby generating a first level LDPC codeword; encoding the second plurality of input bits thereby generating a second level LDPC codeword; grouping at least a first bit of the first level LDPC codeword and at least a first bit of the second level LDPC codeword thereby forming a first sub-block symbol of a plurality of sub-block symbols; grouping at least a second bit of the first level LDPC codeword and at least a second bit of the second level LDPC codeword thereby forming a second sub-block symbol of the plurality of sub-block symbols; symbol mapping the first sub-block symbol of the plurality of sub-block symbols according to a first modulation that includes a first constellation shape and a corresponding first mapping of the plurality of mappings; symbol mapping the second sub-block symbol of the plurality of sub-block symbols according to a second modulation that includes a second constellation shape and a corresponding second mapping of the plurality of mappings; and forming an MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signal, being a sequence of discrete-valued modulation symbols that is mapped using a plurality of mappings, that includes the symbol mapped first sub-block symbol and the symbol mapped second sub-block symbol; processing the MLC LDPC coded modulation signal, if needed, so that it comports with a communication channel; launching the MLC LDPC coded modulation signal into the communication channel. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification