Method and apparatus for designing systems using logic regions

• US 7,197,734 B1
• Filed: 07/12/2002
• Issued: 03/27/2007
• Est. Priority Date: 07/12/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Brown, Stephen D., Vanderhoek, Tim, Hamer, Ivan, Borer, Terry P., Singh, Deshanand P., Guzy, Przemek, Caranci, Steven, Vranesic, Zvonko, Grbic, Alexander, Kuo, Jimmy, Katzin, Rebecca
• Primary Examiner(s): Garbowski; Leigh M.
• Application Number:
  US10/194,199
• Time in Patent Office: 1,719 Days
• Field of Search: 716/16, 716/9, 716/10, 716/12
• US Class Current: 716/116
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first logic region are preserved. The first logic region is integrated with a second logic region having a second component in view of the determined properties.

Claims

1. A method for designing systems on target devices utilizing programmable logic devices (PLDs), comprising:

determining a first position for implementing a component on a first logic region defined by a first user and that groups together a first plurality of components identified by the first user on the PLD;

determining a first location on a target device for implementing the first logic region;

preserving information regarding the first position on the first logic region and the first location on the target device; and

integrating the first logic region with a second logic region defined by a second user and that groups together a second plurality of components identified by the second user in a separate designs in view of the information.

2. The method of claim 1, wherein preserving the information comprises assigning a size and the first location to the first logic region.

3. The method of claim 1, wherein preserving the information comprises assigning the first position on the first logic region to the component.

4. The method of claim 1, wherein preserving the information comprises:

assigning the first position on the first logic region to the component; and

assigning the first location to the first logic region.

5. The method of claim 1, wherein integrating the first logic region with a second logic region in view of the information comprises determining a second location from available space for the second logic region.

6. The method of claim 1, wherein determining the first location on the target device for implementing the first logic region comprises:

assigning an initial location to the first logic region;

moving the first logic region to a new location; and

evaluating a cost function associated with the first logic region in the new location.

7. The method of claim 6, wherein evaluating the cost function comprises:

determining a timing of the system associated with the first logic region in the new location; and

determining routing resources requirements associated with the first logic region in the new location.

8. The method of claim 1, wherein determining the first position on the first logic region for the component and determining the first location on the target device for the first logic region are performed concurrently.

9. The method of claim 8, wherein determining the first position on the first logic region for the component and determining the first location on the target device for the first logic region comprises:

assigning an initial location on the target device to the first logic region;

assigning an initial position on the first logic region to the component; and

evaluating a cost function as the first logic region and the component are moved.

10. A method for designing systems on target devices utilizing programmable logic devices (PLDs), comprising:

determining a first location on a target device for implementing a first logic region defined by a first user and that groups together a first plurality of components on the PLD;

preserving information regarding the first location on the target device; and

integrating the first logic region with a second logic region, defined by a second user in a separate design and that groups together a second plurality of components on the PLD in view of the information.

11. The method of claim 10, wherein preserving the information comprises assigning the first location to the first logic region.

12. The method of claim 10, wherein integrating the first logic region with the second logic region comprises determining a second location from available space for the second logic region.

13. The method of claim 12, wherein integrating the first logic region with the second logic region comprises determining a first position on the second logic region for the second component.

14. The method of claim 10, wherein integrating the first logic region with the second logic region comprises determining a first position on the first logic region for the first component.

15. The method of claim 10, wherein determining the first location on the target device for implementing the first logic region comprises:

assigning an initial location to the first logic region;

moving the first logic region to a new location; and

evaluating a cost function associated with the first logic region in the new location.

16. The method of claim 15, wherein evaluating the cost function comprises:

determining a timing of the system associated with the first logic region in the new location; and

determining routing resources requirements associated with the first logic region in the new location.

17. A method for designing systems on target devices utilizing programmable logic devices (PLDs), comprising:

determining a first position for implementing a first component on a first logic region defined by a first user and that groups together a first plurality of components on the PLD;

preserving information regarding the first position; and

integrating the first logic region with a second logic region, defined by a second user in a separate design and that groups together a second plurality of components on the PLD, in view of the information.

18. The method of claim 17, wherein preserving the information comprises assigning the first position on the first logic region to the first component.

19. The method of claim 17, wherein integrating the first logic region with the second logic region comprises:

determining a first location on a target device for the first logic region; and

determining a second location for the second logic region.

20. The method of claim 19, wherein determining the first location on the target device for implementing the first logic region and determining the second location on the target device for the second logic region are performed concurrently.

21. The method of claim 19, wherein determining the first location on the target device for the first logic region and determining the second location on the target device for the second logic region comprises:

assigning initial locations to the first and second logic regions;

moving the first and second logic regions to new locations; and

evaluating a cost function associated with the first and second logic regions in the new locations.

22. The method of claim 21, wherein evaluating the cost function comprises:

determining a timing of the system associated with the first and second logic regions in the new locations; and

determining routing resources requirements associated with the first and second logic regions in the new locations.

23. A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform the steps of:

determining a first position on a first logic region for a component;

determining a first location on a target device utilizing a programmable logic device (PLD) for the first logic region;

preserving information regarding the first position on the first logic region and the first location on the target device for the first logic region; and

integrating the first logic region with a second logic region defined by a user in separate design in view of the information.

24. The computer-readable medium of claim 23, wherein preserving the information comprises assigning the first location to the first logic region.

25. The computer-readable medium of claim 23, wherein preserving the information comprises assigning the first position on the first logic region to the component.

26. The computer-readable medium of claim 23, wherein preserving the information comprises:

assigning the first position on the first logic region to the component; and

assigning the first location to the first logic region.

27. A method for designing systems on target devices utilizing programmable logic devices (PLDs), comprising:

optimizing placement of a first logic region defined by a first user and that groups together a first plurality of components on the PLD, at a first location on a target device;

preserving information regarding the first location on the target device;

optimizing placement of a second logic region, defined by a second user in a separate design and that groups together a second plurality of components on the PLD, at a second location on the target device, wherein optimizing the placement of the second logic region is performed separately from optimizing the placement of the first logic region; and

integrating the first logic region with the second logic region.

28. The method of claim 27, wherein preserving the information comprises assigning the first location to the first logic region.

29. The method of claim 27, wherein integrating the first logic region with the second logic region comprises determining a second location from available space for the second logic region.

30. A method for designing systems on target devices utilizing programmable logic devices (PLDs), comprising:

determining a first position for implementing a first component on a first logic region defined by a first user and that groups together a first plurality of components on the PLD in a first design;

determining a first location on a target device for implementing the first logic region in the first design;

preserving information in the first design regarding the first position on the first logic region and the first location on the target device;

determining a second position for implementing a second component on a second logic region defined by a second user and that groups together a second plurality of components on the PLD in a second design;

determining a second location on the target device for implementing the second logic region in the second design; and

integrating the first position for implementing the first component and the first location for the first logic region with the second position for implementing the second component and the second location for the second logic region in the second design utilizing the information in the first design.