Semiconductor chip assemblies, methods of making same and components for same

• US 7,198,969 B1
• Filed: 09/07/2000
• Issued: 04/03/2007
• Est. Priority Date: 09/24/1990
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Khandros, Igor Y., Distefano, Thomas H.
• Primary Examiner(s): Graybill; David E.
• Application Number:
  US09/656,690
• Time in Patent Office: 2,399 Days
• Field of Search: 438/33, 438/68, 438/113, 438/458, 438460-465, 438/FOR.386, 438/FOR.387, 438/114, 257/620
• US Class Current: 438/33
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8547 Zirconium (Zr) as principal constituent
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3164 the coating being a foil
• CPC Class Codes: H01L 23/485 : consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49861 : Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Claims

1. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a portion of a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a respective section of a dielectric interposer to each respective one of the plurality of chips individually, without detaching the plurality of chips from the portion of the semiconductor wafer, each section of interposer having a plurality of bonding pads near an outer periphery of the section, such that each bonding pad lies near the contact pattern area of the corresponding one of the plurality of chips;

(c) wire bonding each bonding pad to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

2. A method according to claim 1, wherein step (c) includes bonding one end of each wire to a respective bonding pad using one of the group consisting of micro resistant welding and ultrasonic bonding.

3. A method according to claim 1, wherein step (b) includes providing an elastomer between each of the plurality of chips and the respective interposer on the chip.

4. A method according to claim 1, wherein the portion of the semiconductor wafer includes the whole semiconductor wafer.

5. A method according to claim 1, wherein one end of each wire is bonded to a respective bonding pad of the interposer using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.

6. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a portion of a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a sheet including a plurality of interposers to said portion of said semiconductor wafer so that each said interposer is assembled to an associated one of the plurality of chips, without detaching the plurality of chips from the portion of the semiconductor wafer, each said interposer having a plurality of bonding terminals near an outer periphery of the interposer, such that each bonding terminal of each said interposer lies near the contacts of the one of the plurality of chips associated with that interposer;

(c) wire bonding each bonding terminal to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

7. A method according to claim 6, wherein step (c) includes bonding one end of each wire to a respective bonding terminal using ultrasonic bonding.

8. A method according to claim 6, wherein step (b) includes providing an elastomer between each of the plurality of chips and the interposer associated with that chip.

9. A method according to claim 6, wherein the portion of the semiconductor wafer includes the whole semiconductor wafer.

10. A method according to claim 6, wherein one end of each wire is bonded to a respective bonding terminal of the interposer using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.

11. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a sheet including a plurality of interposers to said semiconductor wafer so that each said interposer is assembled to an associated one of the plurality of chips, without detaching the plurality of chips from the semiconductor wafer, each said interposer having a plurality of bonding terminals near an outer periphery of the interposer, such that each bonding terminal of each said interposer lies near the contacts of the one of the plurality of chips associated with that interposer;

(c) wire bonding each bonding terminal to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

12. A method according to claim 11, wherein step (c) includes bonding one end of each wire to a respective bonding terminal using ultrasonic bonding.

13. A method according to claim 11, wherein step (b) includes providing an elastomer between each of the plurality of chips and the interposer associated with that chip.

14. A method according to claim 11, wherein one end of each wire is bonded to a respective bonding terminal of the interpose using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.

15. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a portion of a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a respective section of a dielectric interposer to each respective one of the plurality of chips individually, without detaching the plurality of chips from the portion of the semiconductor wafer, each section of interposer having a plurality of bonding pads near an outer periphery of the section, such that each bonding pad lies near the contact pattern area of the corresponding one of the plurality of chips;

(c) wire bonding each bonding pad to a respective one of the contacts on the front surface of the corresponding one of the plurality of chip whereby wires extend from the bonding pads to the contacts;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

16. A method according to claim 15, wherein step (c) includes bonding one end of each one of said wires to a respective bonding pad using one of the group consisting of micro resistant welding and ultrasonic bonding.

17. A method according to claim 15, wherein step (b) includes providing an elastomer between each of the plurality of chips and the respective interposer on the chip.

18. A method according to claim 15, wherein the portion of the semiconductor wafer includes the whole semiconductor wafer.

19. A method according to claim 15, wherein one end of each wire is bonded to a respective bonding pad of the interposer using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.

20. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a portion of a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a sheet including a plurality of interposers to said portion of said semiconductor wafer so that each said interposer is assembled to an associated one of the plurality of chips, without detaching the plurality of chips from the portion of the semiconductor wafer, each said interposer having a plurality of bonding terminals near an outer periphery of the interposer, such that each bonding terminal of each said interposer lies near the contacts of the one of the plurality of chips associated with that interposer;

(c) wire bonding each bonding terminal to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips whereby wires extend from the bonding pads to the contacts;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

21. A method according to claim 20, wherein step (c) includes bonding one end of each one of said wires to a respective bonding terminal using ultrasonic bonding.

22. A method according to claim 20, wherein step (b) includes providing an elastomer between each of the plurality of chips and the interposer associated with that chip.

23. A method according to claim 20, wherein the portion of the semiconductor wafer includes the whole semiconductor wafer.

24. A method according to claim 20, wherein one end of each wire is bonded to a respective bonding terminal of the interposer using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.

25. A method of assembling a plurality of semiconductor chips, comprising the steps of:

(a) providing a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip;

(b) assembling a sheet including a plurality of interposers to said semiconductor wafer so that each said interposer is assembled to an associated one of the plurality of chips, without detaching the plurality of chips from the semiconductor wafer, each said interposer having a plurality of bonding terminals near an outer periphery of the interposer, such that each bonding terminal of each said interposer lies near the contacts of the one of the plurality of chips associated with that interposer;

(c) wire bonding each bonding terminal to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips whereby wires extend from the bonding pads to the contacts;

(d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and

(e) cutting the encapsulated chips from the semiconductor wafer.

26. A method according to claim 25, wherein step (c) includes bonding one end of each one of said wires to a respective bonding terminal using ultrasonic bonding.

27. A method according to claim 25, wherein step (b) includes providing an elastomer between each of the plurality of chips and the interposer associated with that chip.

28. A method according to claim 25, wherein one end of each wire is bonded to a respective bonding terminal of the interpose using ultrasonic bonding, and the other end of each wire is bonded to a respective contact of the chip using ultrasonic bonding.