Methods for assembling multiple semiconductor devices

• US 7,198,980 B2
• Filed: 11/12/2003
• Issued: 04/03/2007
• Est. Priority Date: 06/27/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Chye, Lim Thiam, Yean, Tay Wuu, Fee, Setho Sing
• Primary Examiner(s): Whitehead, Jr.; Carl
• Assistant Examiner(s): Dolan; Jennifer M.
• Application Number:
  US10/706,576
• Publication Number:
  US 20040106229A1
• Time in Patent Office: 1,238 Days
• Field of Search: 257/723, 257/724, 257/777, 257/778, 257/782, 257/786, 257/E23.169, 257/E23.175, 438/106, 438/107, 438/108, 438/109
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/045 : Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
• CPC Class Codes: H05K 2201/049 : PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 : Notches in edge pads
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Claims

1. A method for assembling a multidie semiconductor device package, comprising:

providing an interposer with a substantially planar substrate and a receptacle formed substantially through the substrate, the substrate having an upper surface and a lower surface, at least the upper surface having conductors thereon;

positioning at least one first-level semiconductor device within the receptacle, a backside of the at least one first-level semiconductor device being substantially coplanar with the lower surface of the substrate or located within a plane which extends through the substrate an interstitial space remaining at least between peripheral edges of the at least one first-level semiconductor device and the substrate;

positioning a second-level semiconductor device above the upper surface of the substrate, a portion of the second-level semiconductor device superimposed with the upper surface of the substrate;

electrically connecting the at least one first-level semiconductor device to at least the conductors on the upper surface of the substrate by first-level conductive members that include laterally extending portions that are at least partially carried by a surface of the second-level semiconductor device; and

electrically connecting the second-level semiconductor device to the conductors on the upper surface of the substrate by second-level conductive members.

2. The method of claim 1, further comprising introducing a quantity of encapsulant material into the receptacle so as to fill at least a portion of the interstitial space.

3. The method of claim 2, wherein the introducing encapsulant material is effected after the electrically connecting the at least one first-level semiconductor device.

4. The method of claim 2, further comprising introducing a quantity of encapsulant material between the second-level semiconductor device and the at least one first-level semiconductor device.

5. The method of claim 2, further comprising adhering a film to the lower surface of the substrate to cover at least a portion of the receptacle prior to positioning the at least one first-level semiconductor device therein.

6. The method of claim 5, further comprising removing the adhered film from the lower surface following curing of the encapsulant material in the receptacle.

7. The method of claim 1, wherein electrically connecting the at least one first-level semiconductor device comprises forming or positioning intermediate conductive elements between bond pads of the at least one first-level semiconductor device and corresponding conductors of the interposer.

8. The method of claim 1, wherein electrically connecting the second-level semiconductor device comprises forming or positioning intermediate conductive elements between bond pads of the second-level semiconductor device and corresponding conductors of the interposer.

9. The method of claim 1, wherein positioning the second-level semiconductor device comprises at least one of positioning the second-level semiconductor device in a flip-chip arrangement over the at least one first-level semiconductor device and positioning the second-level semiconductor device over the interposer.

10. The method of claim 9, further comprising securing the at least one first-level semiconductor device and the second-level semiconductor device to one another before the positioning the second-level semiconductor device.

11. The method of claim 1, wherein the providing the interposer comprises providing a multi-interposer substrate on which the at least one first-level semiconductor device and the second-level semiconductor device are positioned and electrically connected.

12. The method of claim 11, further comprising singulating individual assemblies or packages from the multi-interposer substrate.

13. The method of claim 1, further comprising positioning another first-level semiconductor device within the receptacle, a backside of the another first-level semiconductor device facing the backside of the at least one first-level semiconductor device.

14. The method of claim 13, further comprising electrically connecting bond pads of the another first-level semiconductor device to corresponding conductors on the lower surface of the substrate.

15. The method of claim 13, further comprising positioning a third-level semiconductor device over the lower surface of the substrate.

16. The method of claim 15, further comprising electrically connecting bond pads of the another first-level semiconductor device to corresponding bond pads of the third-level semiconductor device.

17. The method of claim 15, further comprising electrically connecting bond pads of the third-level semiconductor device to corresponding conductors on the lower surface of the substrate.

18. A method for assembling semiconductor device components, comprising:

providing an interposer with a substantially planar, substantially rigid substrate and a receptacle formed substantially through the substrate;

positioning a first semiconductor device over a first surface of the interposer, at least one bond pad of the first semiconductor device being exposed to the receptacle;

positioning a second semiconductor device over a second surface of the interposer, at least one bond pad of the second semiconductor device being exposed to the receptacle; and

electrically connecting the at least one bond pad of the first and second semiconductor devices through the receptacle; and

electrically connecting at least the first semiconductor device to the interposer, at least a laterally extending portion of one conductive element carried by a surface of the first semiconductor device, also facilitating electrical connection of the second semiconductor device to the interposer upon electrically connecting the at least the first semiconductor device thereto.

19. The method of claim 18, wherein electrically connecting includes securing a conductive structure to the at least one bond pad of the first semiconductor device or to the at least one bond pad of the second semiconductor device.

20. The method of claim 19, wherein securing is effected before positioning.

21. The method of claim 19, wherein securing is effected following positioning.

22. The method of claim 18, wherein positioning the first semiconductor device comprises positioning the first semiconductor device with the at least one bond pad exposed to the receptacle comprising a portion of a redistribution circuit on a surface of the first semiconductor device.