Multi-strand substrate for ball-grid array assemblies and method

• US 7,199,306 B2
• Filed: 12/19/2003
• Issued: 04/03/2007
• Est. Priority Date: 12/05/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Owens, Norman Lee
• Primary Examiner(s): Dinh, Tuan
• Application Number:
  US10/741,065
• Publication Number:
  US 20040129452A1
• Time in Patent Office: 1,201 Days
• Field of Search: 174/52.2, 174260-262, 361782-784, 361803-804, 257787-790, 29840-842
• US Class Current: 174/260
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 2201/09063 : Holes or slots in insulating substrate not used for electrical connections
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/0097 : Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49222 : forming array of contacts or terminals

Abstract

A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

Claims

1. A method for assembling ball-grid array (BGA) packages, comprising the steps of:

providing a plurality of BGA substrates arranged in an N by M array within a printed circuit board having a thickness, wherein N and M are greater than or equal to 2, each of the plurality of BGA substrates having a plurality of bond posts and a plurality of contact pads;

attaching a semiconductor die to each of the plurality of BGA substrates, the semiconductor die having a plurality of bond pads;

encapsulating the semiconductor die with an encapsulant;

curing the encapsulant; and

dividing the N by M array into separate BGA packages, wherein the size of the N by M array and the thickness of the printed circuit board are selected such that each of the plurality of BGA substrates maintains a planarity variation less than approximately 0.15 mm after assembly.

2. The method of claim 1, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a plurality of stress-relief slots at various locations within the printed circuit board.

3. The method of claim 1, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a thickness greater than approximately 0.5 mm.

4. The method of claim 1, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a width on an order of 63 mm.

5. The method of claim 1, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a length in a range from approximately 187 mm to 212 mm.

6. The method of claim 1 further comprising the steps of:

bonding conductive wires to the plurality of bond pads and the plurality of bond posts after the step of attaching the semiconductor die; and

marking the BGA packages after the step of encapsulating the semiconductor die.

7. The method of claim 1, wherein the step of curing the encapsulant further includes protecting the plurality of contact pads from foreign matter contamination.

8. The method of claim 1, wherein a semiconductor die is attached to each of the plurality of BGA substrates using a die attach pad comprising copper or gold plated copper.

9. The method of claim 1, wherein a semiconductor die is attached to each of the plurality of BGA substrates using a die attach pad and wherein the die attach pad is a solid metallization area.

10. The method of claim 1, wherein a semiconductor die is attached to each of the plurality of BGA substrates using a die attach pad and wherein the die attach pad is a patterned metallization area having a specific geometric shape, wherein the specific geometric shape is a cross or Union Jack.

11. The method of claim 1 further comprising attaching conductive solder balls to each of the plurality of contact pads.

12. The method of claim 1, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a plurality of stress-relief slots at various locations within the printed circuit board.

13. The method of claim 1, wherein the plurality of bond posts are on one side of the each of the plurality of BGA substrates and the plurality of contact pads are on an opposite side of the each of the plurality of BGA substrates.

14. The method of claim 1, wherein the printed circuit board comprises at least one of a bismaleimide-triazin (BT) resin and a FR-board.

15. The method of claim 1, wherein the step of encapsulating the semiconductor die with an encapsulant comprises using one of an over-molding process or a glob-top process.

16. The method of claim 1, wherein the encapsulant comprises at least an organic material.

17. The method of claim 1, wherein the printed circuit board further comprises a plurality of alignment holes along only one edge of the printed circuit board.

18. The method of claim 1, wherein the printed circuit board further comprises a plurality of alignment holes along only two edges of the printed circuit board.

19. The method of claim 1, wherein each of the plurality of BGA substrates corresponds to an individual device.

20. The method of claim 2, wherein at least one of the plurality of stress-relief slots is of a different size from another of the plurality of stress-relief slots.

21. The method of claim 11 further comprising removing at least some corrosive residue from the printed circuit board after attaching conductive solder balls to each of the plurality of contact pads.

22. The method of claim 11, wherein attaching conductive solder balls to each of the plurality of contact pads comprises attaching the conductive solder balls at room temperature.

23. The method of claim 11 further comprising reflowing the conductive solder balls using an automated solder reflow process after attaching the conductive solder balls.

24. The method of claim 12, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a thickness greater than approximately 0.5 mm.

25. The method of claim 12, wherein at least one of the plurality of stress-relief slots is of a different size from another of the plurality of stress-relief slots.

26. The method of claim 19, wherein each of the individual devices comprises a semiconductor die.

27. The method of claim 24, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a width on an order of 63 mm.

28. The method of claim 27, wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a length in a range from approximately 187 mm to 212 mm.

29. The method of claim 28 further comprising the steps of:

bonding conductive wires to the plurality of bond pads and the plurality of bond posts after the step of attaching the semiconductor die; and

marking the BGA packages after the step of encapsulating the semiconductor die.

30. The method of claim 29, wherein the step of curing the encapsulant further includes protecting the plurality of contact pads from foreign matter contamination.