Pixel structure with improved charge transfer

• US 7,199,410 B2
• Filed: 12/13/2000
• Issued: 04/03/2007
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dierickx, Bart
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US09/736,651
• Publication Number:
  US 20010011736A1
• Time in Patent Office: 2,302 Days
• Field of Search: 257/233, 257/234, 257/215, 257/222, 257/225, 257/236, 257237-239, 257/E27.082
• US Class Current: 257/233
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H01L 31/0352 characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/585 with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Claims

1. A pixel structure comprising:

a semiconductor substrate;

a radiation sensitive source of carriers in the substrate;

a region in the substrate for collecting but not storing the carriers;

at least one doped or inverted region of a first conductivity in or on the substrate; and

at least one planar current flow, carrier transport pathway from or through the region in the substrate for collecting but not storing carriers, to the at least one doped or inverted region, in which carrier transport pathway carriers are not stored, there being no means for storing carriers in between the region for collecting but not storing carriers and the at least one planar current flow, carrier transport pathway, wherein substantially all of the region for collecting but not storing carriers is under a polysilicon gate electrode.

2. The pixel structure according to claim 1, wherein the non-carrier storing, carrier collecting region has a concentration so low that it is in normal use always depleted.

3. The pixel structure according to claim 2, wherein at least part of the non-carrier storing, carrier collecting region is a pinned or buried diode.

4. The pixel structure according to claim 1, wherein the non-carrier storing, carrier collecting region is substrate under a covering oxide layer.

5. The pixel structure according to claim 1, wherein the non-carrier storing, carrier collecting region is substrate under a field oxide layer.

6. The pixel structure according to claim 1, wherein the region for collecting but not storing carriers is diffusion limited.

7. The pixel structure according to claim 1, further comprising at least one implant confining the region for collecting but not storing carriers along at least one dimension thereof.

8. The pixel structure according to claim 1, further comprising regions of a second conductivity type in or on the substrate avoiding touching of the region for collecting but not storing carriers and a field oxide.

9. The pixel structure according to claim 1, wherein the pixel is MOS-based.