Non-volatile memory cells

• US 7,199,425 B2
• Filed: 02/04/2004
• Issued: 04/03/2007
• Est. Priority Date: 05/26/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Primary Examiner(s): Ngô; Ngân V.
• Application Number:
  US10/770,579
• Publication Number:
  US 20040238881A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257/315, 257/316, 257/317, 257/E29.129
• US Class Current: 257/317
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate provided with an isolation trench filled with an isolation film; and

a plurality of non-volatile memory cells provided on the semiconductor substrate, each of the plurality of non-volatile memory cells comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in a channel width direction, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode,

wherein the plurality of non-volatile memory cells includes a first non-volatile memory cell including a first floating gate electrode and a second non-volatile memory cell, adjacent to the first non-volatile memory cell, including a second floating gate electrode, the isolation film covers lower side portions of the first and second floating gate electrodes in the channel width direction, and the widths of the first and second floating gate electrodes gradually increase, in the channel width direction, toward the lower surfaces of the first and second floating gate electrodes from the upper surface of the isolation film.

2. The semiconductor device according to claim 1, wherein the width of the floating gate electrode is the thinnest at an approximately intermediate position between the region above the bottom surface of the floating gate electrode and the region below the upper surface thereof.

3. The semiconductor device according to claim 1, wherein the width of the floating gate electrode gradually increases toward the upper and lower surfaces of the floating gate electrode from the position where the width of the floating gate electrode is the thinnest.

4. The semiconductor device according to claim 2, wherein the width of the floating gate electrode gradually increases toward the upper and lower surfaces of the floating gate electrode from the position where the width of the floating gate electrode is the thinnest.

5. The semiconductor device according to claim 3, wherein the width of the floating gate electrode nonlinearly increases.

6. The semiconductor device according to claim 4, wherein the width of the floating gate electrode nonlinearly increases.

7. The semiconductor device according to claim 1, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

8. The semiconductor device according to claim 2, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

9. The semiconductor device according to claim 3, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

10. A semiconductor device according to claim 1, wherein the width of the floating gate electrode in channel length direction is substantially uniform.

11. A semiconductor device according to claim 1, wherein the width of the part of the side portion is thinner than a bottom width of the first floating gate electrode.

12. A semiconductor device according to claim 1, wherein the floating gate electrode includes a top surface which is higher than that of the isolation film in the channel width direction.

13. A semiconductor device according to claim 1, wherein the isolation film further covers upper side portions of the first and second floating gate electrodes in the channel width direction, widths of the first and second floating gate electrodes in the channel width direction are the thinnest at an approximately intermediate position in a height direction of the first and second floating gate electrodes, and the widths of the first and second floating gate electrodes gradually increase toward bottom side and top side surfaces of the first and second floating gate electrodes from the intermediate position.