Integrated switchless programmable attenuator and low noise amplifier

• US 7,199,664 B2
• Filed: 12/27/2004
• Issued: 04/03/2007
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gomez, Ramon A., Bult, Klaas
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US11/020,478
• Publication Number:
  US 20050107055A1
• Time in Patent Office: 827 Days
• Field of Search: 330/144, 330/254, 330/284, 333/81.R
• US Class Current: 330/284
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. A circuit comprising:

a) a variable potentiometer having a plurality of tap points; and

b) a plurality of differential amplifiers;

wherein each differential amplifier includes a pair of transistors with a first gate directly connected to ground, a second gate coupled to a tap point of said variable potentiometer and sources coupled to each other.

2. The circuit of claim 1, wherein each differential amplifier is selectively controlled by at least one variable control signal generator coupled to said sources of said transistors.

3. The circuit of claim 2, wherein said variable control signal generator is a variable tail current generator.

4. The circuit of claim 1, wherein said variable potentiometer includes a resistor ladder network having multiple tap points, each tap point providing a differing value of attenuation.

5. The circuit of claim 4, wherein each differential amplifier of said plurality of differential amplifiers is selectively turned on, individually or as a group, to amplify an attenuated signal from said variable potentiometer.

6. The circuit of claim 2, wherein said variable control signal generator generates a control signal by sampling sync pulses of a base band television signal and averaging amplitude of said sync pulses over a specific period of time.

7. The circuit of claim 1, wherein as said variable potentiometer setting changes, a signal level at an input to a differential amplifier changes accordingly, thereby changing an output accordingly.

8. The circuit of claim 1, further comprising:

a single input port coupled to said variable potentiometer and configured to receive a signal and an output port coupled to a differential amplifier of said plurality of differential amplifiers and configured to transmit a differential signal.

9. The circuit of claim 1, wherein said variable potentiometer includes resistors configured as multiple pi sections such that a constant impedance is presented to a signal source.

10. The circuit of claim 9, wherein a tap point of said variable potentiometer is a pi section connected to said second gate.

11. The circuit of claim 1, wherein outputs of said differential amplifiers are tied in parallel, wherein a resulting output is a parallel combination of one or more activated differential amplifiers.

12. The circuit of claim 2, wherein said variable control signal generator emulates a sliding multiple contact switch by turning a differential amplifier tail current off at one end of a chain of said differential amplifiers and on at another end of said chain of differential amplifiers so as to adjust attenuation to a desired value.

13. A circuit comprising:

a) a variable potentiometer having a plurality of tap points; and

b) a plurality of differential amplifiers;

wherein each differential amplifier includes a pair of transistors with a first gate coupled to ground, a second gate coupled to a tap point of said variable potentiometer and sources coupled to each other; and

wherein a noise figure for at least one of said differential amplifiers is lowered by introducing a sufficient bias current to increase a transconductance associated with said differential amplifier, wherein said transconductance decreases said noise figure of said differential amplifier.

14. A circuit comprising:

a) a variable potentiometer having a plurality of tap points; and

b) a plurality of differential amplifiers;

wherein each differential amplifier includes a pair of transistors with a first gate coupled to ground, a second gate coupled to a tap point of said variable potentiometer and sources coupled to each other; and

wherein control signals are used to program said variable potentiometer to various levels of attenuation and thereby provide output signal smoothness control.

15. A method of variable amplification, using a variable potentiometer, at least one control signal generator, multiple differential amplifiers each including a pair of transistors with a first gate coupled to ground, a second gate coupled to a tap point of said variable potentiometer, sources coupled to said control signal generator, comprising:

a) receiving a signal;

b) attenuating said signal using said variable potentiometer that includes a resistor ladder network having multiple tap points, each providing a differing value of attenuation; and

c) amplifying said attenuated signal by selectively using said differential amplifiers, individually or as a group, said amplifying step including connecting each of said differential amplifiers to a corresponding different tap point of said ladder network and selectively turning on said differential amplifiers, individually or as a group, using said control signal generator, so as to amplify said attenuated signal;

wherein each of said differential amplifiers are selectively controlled by said control signal generator; and

wherein said control signal generator is a variable tail current generator.

16. A circuit, comprising:

a) means for receiving a signal;

b) means for attenuating said received signal producing multiple attenuated outputs;

c) means for selectively amplifying said multiple attenuated outputs, individually or as a group, producing multiple amplified outputs; and

d) means for combining said multiple amplified outputs;

wherein said means for attenuating includes multiple tap points, each providing a differing value of attenuation; and

wherein said means for amplifying is connected to a corresponding different tap point and selectively turned on individually or as a group using at least one of said control signal generators, to amplify an attenuated output.

17. The circuit of claim 16, wherein said means for selectively amplifying is controlled by at least one control signal generator.